AD9695 Multichip Sync

Does anybody have an idea?

Hi enginoob,

I've done some readings about this. 

Yes, it is possible to use SYSREF for the ADC side only (assuming this SYSREF will be coming from the FPGA), however it should use and synchronize to the main/system sample clock that is also sent to the ADCs, it will be difficult to phase align the SYSREF signal from the logic device (assuming from an FPGA) to the clock. Thus, in some applications, the approach it to provide SYSREF from a separate clock generation circuit so that the phase alignment of multiple clocks throughout the system can be better achieved. *based from reference 1*

Here are some references you can check that discusses more about this:
1. Synchronizing Multiple ADCs Using JESD204B | Analog Devices
2. JESD204B Subclasses—Part 1: An Introduction to JESD204B Subclasses and Deterministic Latency | Analog Devices

On the AD9695 datasheet, discussion specific to the part starts at page 83.

I hope this helps.

Best regards,
Peevee

Hi enginoob,

I've done some readings about this. 

Yes, it is possible to use SYSREF for the ADC side only (assuming this SYSREF will be coming from the FPGA), however it should use and synchronize to the main/system sample clock that is also sent to the ADCs, it will be difficult to phase align the SYSREF signal from the logic device (assuming from an FPGA) to the clock. Thus, in some applications, the approach it to provide SYSREF from a separate clock generation circuit so that the phase alignment of multiple clocks throughout the system can be better achieved. *based from reference 1*

Here are some references you can check that discusses more about this:
1. Synchronizing Multiple ADCs Using JESD204B | Analog Devices
2. JESD204B Subclasses—Part 1: An Introduction to JESD204B Subclasses and Deterministic Latency | Analog Devices

On the AD9695 datasheet, discussion specific to the part starts at page 83.

I hope this helps.

Best regards,
Peevee

Yes, this helps immensely. Thank you so much, Peevee! You're a lifesaver. 

Peevee, as a follow-up question, we can't feed a SYSREF clock only to the FPGA right? It's either FPGA and ADC or just ADC?

Peevee, I have also been reading about sysref and subclasses. I understand that subclass 1 utilizes SYSREF on both the jesd204b receiver an transmitter. If I wanted to implement a system using subclass 1, would I have to connect a sysref clock to both the adc and fpga?

Yes, it's either FPGA and ADC or just the ADC (Timestamp mode)

Yes. You should have something similar to what is shown in Synchronizing Multiple ADCs Using JESD204B | Analog Devices