I am trying to capture the data outputs of two AD9695-1300 chips on the ZCU102 FPGA. I have been going through the datasheet and reference design using the ZCU102, and I had a question on the multichip sync feature.
I understand that in subclass 1, we can use the SYSREF clock to set a timestamp in a 16 bit sequence. On the reference design page a sysref clock was connected to both the ADC and FPGA.
Why do we connect a SYSREF clock to both the ADC and the FPGA? If the SYSREF is simply being used to set a timestamp, can't it be just used on one of the two and have the FPGA align the data?
I ask this because if we have two different clocks feeding into the ADC and FPGA, doesn't that leave both susceptible to timing mismatches/delays between the two clocks?