AD9695 Multichip Sync

Question

I am trying to capture the data outputs of two AD9695-1300 chips on the ZCU102 FPGA. I have been going through the datasheet and reference design using the ZCU102, and I had a question on the multichip sync feature. 
 
 I understand that in subclass 1, we can use the SYSREF clock to set a timestamp in a 16 bit sequence. On the reference design page a sysref clock was connected to both the ADC and FPGA. 
 Why do we connect a SYSREF clock to both the ADC and the FPGA? If the SYSREF is simply being used to set a timestamp, can't it be just used on one of the two and have the FPGA align the data? 
 I ask this because if we have two different clocks feeding into the ADC and FPGA, doesn't that leave both susceptible to timing mismatches/delays between the two clocks?

PeeveeS · Accepted Answer

Hi enginoob,

I've done some readings about this.

Yes, it is possible to use SYSREF for the ADC side only (assuming this SYSREF will be coming from the FPGA), however it should use and synchronize to the main/system sample clock that is also sent to the ADCs, it will be difficult to phase align the SYSREF signal from the logic device (assuming from an FPGA) to the clock. Thus, in some applications, the approach it to provide SYSREF from a separate clock generation circuit so that the phase alignment of multiple clocks throughout the system can be better achieved. *based from reference 1*

Here are some references you can check that discusses more about this:
1. Synchronizing Multiple ADCs Using JESD204B | Analog Devices
2. JESD204B Subclasses—Part 1: An Introduction to JESD204B Subclasses and Deterministic Latency | Analog Devices

On the AD9695 datasheet, discussion specific to the part starts at page 83.

I hope this helps.

Best regards,
Peevee

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AD9695 Multichip Sync