Phase noise and aperture jitter in the AD9081

Question

Hello, 
 We have a few questions about the phase noise and aperture jitter in the AD9081. Our questions below relate to the AD9081 data sheet Rev. 0. 
 1. How are the tones in figures 26-28 generated? Are they generated via ADC input or via internal DDS? 
 2. How is the aperture jitter listed in Table 8 disambiguated from broadband PLL jitter? It would seem to me that if an SNR degradation method were used, one could not perform such a disambiguation and that this aperture jitter number must necessarily include broadband PLL jitter. Over what bandwidth is this SNR degradation method used? 
 3. How were figures 26-28 measured? Were they measured with a spectrum analyzer or a phase noise analyzer? 
 4. Is Fig. 26 with the clock PLL enabled or disabled? 
 5. Fig. 26 seems to indicate the presence of a thermal noise floor unrelated to clock phase noise at -165dBc/Hz, where fout=0MHz. Is this noise floor also present in the measurement of Figs. 27 and 28? 
 6. What output power level in dBFS was used to generate Fig. 26-28? 
 7. Would the curve for Fig. 24 look the same if a -3dBFS digital backoff signal were used for the output? 
 Thanks in advance for any help you can provide! 
 Best Regards, 
 EK14353

FormerMember · Accepted Answer

Hello, Answers to your questions are as follows: 
 1) Phase noise plots are generated by the Tx main data path quadrature modulator NCO (i.e. DDS) generating a tone at the specified frequency with PLL enabled or disabled. 
 2) Footnote 2 for Table 8 describes the conditions used to calculate the jitter of the CLK driving the ADC. The jitter spec quoted for ADC is with both clock and ADC input driven by high quality R&S .SMA100B signal generators. The additive noise degradation due to jitter is calculated by subtracting out thermal noise contribution and the RF input frequency is chosen such that the total noise floor is several dB higher than thermal noise itself. This method calculates the broadband jitter since all broadband phase noise artifacts will alias into the Nyquist range. 
 Note that the jitter of this ADC clock is higher than the DAC clock (using external RF clock from R&S SMA100B) since the divider used to generate the ADC clock adds jitter. If PLL is used to generate DAC clock (and divided down ADC clock), the jitter is dominated by the on-chip PLL/VCO. 3) Phase Noise Analyzer. 
 4) PLL disabled. 
 5) Figure 26 is NSD at 10% offset from fundamental and is usually in region measuring the broadband phase noise (when it levels off) as well as thermal noise floor of DAC. While the phase noise analyzer has ability to include both AM and PM (also combined)..................plots are showing only phase noise. 
 6) Power is around -2 dBm level with DAC's IOUTFS=26 mA , 0 dBFS digital CW waveform, and Marki-balun loss also included when referring to figure 24 plot for 12 GHz DAC operation and 1.8 GHz output. 7) The same frequency response would remain the same but power level would drop by 3 dB. Regards)

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Phase noise and aperture jitter in the AD9081