Question about ADC LTC2175-14 SFDR testing.

Question

During LTC2175-14 hardware testing(work in 125Msps,14bits output), I find that fft-analysis of input signal(sine single-tone, serval frequency in pictures, test instrument: RSA100 Generator, 8k-points fft with window-function) SFDR is abnormal. There are many unknown harmonics regularly in frequency spectrum. The distribution of harmonics seems to be related to the frequency of the input signal. I used to suspect it was reason of the input clock. When I changed the pins of the FPGA(MRCC pins, LVDS_25) to output the clock signal to the ADC, it was still a similar phenomenon. PS.ADC LVDS data parsing is sure to be ok.The output pattern in test code has been verified accuracy.

FormerMember · Accepted Answer

Hi, 
 I observed from your plot that the noise floor is somewhat elevated as well. I have few suggestions to check. 
 1. Use a clean signal generator for the analog input. Probe analog input pins and check if within the desired amplitude level. We also advise to use bandpass filter for best results. 
 2. Clock is another noise source. It is important to have a low jitter clock source as not to limit SNR performance. Refer to this article Maximum SNR vs Clock Jitter | Analog Devices . 
 3. Lastly, can you check if there's an improvement when increasing FFT size? 
 Regards, 
 Meriam)

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Question about ADC LTC2175-14 SFDR testing.