SPI reading issues in AD9653 ADC configuration register.

Hi MoniDeena,

Thanks for your interest in AD9653.

I recommend the following steps:

• Monitor the MISO, MOSI, and SDIO lines using oscilloscope to check expected behavior.
• Try to replace the pull-up resistor R10 to lower values like R7 value; the open-drain buffer might be having difficulty pulling down the line due to high pull-up resistor value.

Thank you.

Regards,

Xavier

Hi Xavier,

Thanks for your reply.

• We have monitored MISO, MOSI and SDIO lines using oscilloscope. The data we have generated in MOSI getting to SDIO properly, but we aren't getting any response in the SDIO line from ADC.
• We have configured the internal reference voltage in ADC and we are getting the exact ref voltage (1V) internal and Vpp = 2V as mentioned in the datasheet.
• Is there any recommended Register Programming Sequence for SPI configuration?
• We didn't generate the sample clock to ADC. So, is there any chance that ADC is not READBACK because of the source clock?

Thanks & Regards,

MoniDeena

Hi MoniDeena,

Have you tried to replace the 27kohm resistor of R10 to lower values like that of R7 and monitor the line?

Regards,

Xavier

Hi Xavier,

I have replaced the 27kohm into 1kohm resistor in R10 and i have monitored MISO, MOSI and SDIO using oscilloscope. In MOSI line we are getting the exact data which we are given and it's also flowing in SDIO line. But we are not able to READBACK the data in SDIO line from the ADC. So, there will be no data in MISO line.

Thanks & Regards,

MoniDeena

Hi MoniDeena,

Could you confirm the following:

1. In MOSI, there is no pull-up in the input side of the buffer. Could you confirm if the pull-up is on the FPGA/controller side?
2. During Idle state of the MOSI line, is it low? If it is idle low, could you try changing to idle high? This is to keep the open-drain buffer connected to MOSI in high-Z state when you are doing read transaction with MISO line.

Thank you and regards,

Xavier