Two AD9208 are configured for working DDC2(decimation 2) mode. Both the ADC's are configured for the same NCO (FTW) setting.
Problem :
The phase of output data between Core0 of ADC0, Core1 of ADC0, Core0 of ADC1, Core1 of ADC1 is not consistent from power on to power on,
It is varying for every synchronization event for the same NCO
AD9208 operational settings
Fs : 2300 MHz
M = 2, L = 8, N’ = 16, S=2, F=1
Lane rate : 5750 MSPS
LMFC clk = 2.246 MHz
Mode : DDC 2(decimation by 2), Real output,
Core0 connected to DDC0
Core1 connected to DDC1
NCO is operated in phase coherent mode.
NCO frequency : 1290 MHz.
FTW : 0x8F95 25D7 EE30
Sysref frequency : 2300/0x400 = 2.246 MHz
Register settings for both ADC’s
|
Register Address |
Data set |
Remarks |
|
0x0120 |
0x52 |
Resetting the Sys_ref counter, sysref is valid on high to low transition, sysref is captured on rising edge of clk±, sysref mode is continuous |
|
0x0120 |
0x12 |
|
|
0x0121 |
0x00 |
Next sysref only |
|
0x0122 |
0x00 |
No skew applied |
|
0x0300 |
0x93 |
FTW/POW values are updated synchronously when the chip transfer bit (Register 0x000F, Bit 0) is set, DDC held in reset. Only the next valid edge of the SYSREF± pin is used to synchronize the NCO in the DDC block. If DDC next synchronization (Register 0x0300, Bit 1 = 1), only the next valid edge of the SYSREF± pin is used to synchronize the NCO in the DDC block. |
|
0x01FF |
0x00 |
JESD synchronization. |
|
|
|
|
HMC7044 settings
Sysref is generated using clkout5 and clkout7. The following are the setting
|
Register Address |
Data set |
Remarks |
|
0x005A |
0x01 |
No of sysref pulses : 1 |
|
0x0110 |
0x04 |
MSB of the divider is set to be 4 for sysref pulses |
|
0x0111 |
0x10 |
Analog fine delay of 16 * 25psec is applied |
|
0x0115 |
0x01 |
Analog delay output is selected |
|
0x0116 |
0x88 |
Output is forced to zero, output is configured to be LVDS |
|
0x00FA |
0xFD |
Channel is enabled |
|
0x00FC |
0x04 |
MSB of the divider is set to be 4 for sysref pulses |
|
0x00FD |
0x00 |
Zero analog delay |
|
0x0101 |
0x00 |
Clock diver output is selected |
|
0x0102 |
0x88 |
Output is forced to zero, output is configured to be LVDS |
|
|
|
|
Sequence of operation:
- Sysref counter is reset
- Sysref is programmed using the 0x0120 with the following
- Sysref is valid on high to low transition
- Sysref is captured using rising edge of clk±
- Sysref mode is continuous
- No skew is applied using register 0c0122
- NCO is reset using 0x0300 register bit 4
- NCO FTW is updated using chip transfer register.
- NCO synchronization using 0x0300 bit 0 & bit 1 is setup
- Sysref is generated using HMC7044.
Status read back
|
Register Address |
Data read |
Remarks |
|
0x0128 |
0x8D |
For ADC0 |
|
0x0128 |
0x8E |
For ADC1 |
|
0x0129 |
0x00 |
For Both ADC0 & ADC1 |
|
0x012A |
|
Is incremented for every sysref event. |
|
0x0300 |
0x82 |
For both ADC0 & ADC1 |
Request to provide a procedure and register settings for NCO synchronization across multichip configuration of AD9208
