I am evaluating an AD9680 and have an inquiry regarding the minimum lane line rate.
I had setup the device with 2 lanes, single converter and sample size (N') of 16. I then operate the sample clock at 300MSPS. The calculated sample rate is therefore 3Gbps
L = 2
N' = 16
M = 1
F_ADC_CLOCK = 300MSPS
I did not notice that the datasheet specify that the minimum line lane rate is 3.125Gbps, however, my receiver (based on a Xilinx Ultrascale FPGA) seems to work perfectly fine and does not detect and bit errors.
Where does the 3.125Gbps limitation come from?
It seems to imply that running at 300MSPS with a single converter at N' = 8 is impossible no matter how many lanes are used for the link.
Edited to add a comment about running at 300MSPS with N' = 8
[edited by: eniv at 9:29 PM (GMT -5) on 28 Nov 2022]