Sample Rate about AD9689

Question

Hi, 
 According to the AD9689 datasheet description, the AD9689 can provide a total clock fine delay of 363.2ps (Register 0x0111,0x0112), 
 
 Then suppose I let AD9689 work at 2500MHz(T=400ps) and delay the clock phase of CH.B 200ps behind CH.A, as shown in Figure. 93(spec page 34). 
 Is this equivalent to the alternating work of CH.A and CH.B? Like TIADC. 
 The sampling rate can reach 5Gsps? 
 
 Thanks in advance for your help. 
 
 Regards, 
 Kyle

PeeveeS · Accepted Answer

Hi Kyle,

Thank you for your interest in AD9689.

The AD9689 is designed for simultaneous sampling at 2.0 GSPS/2.6 GSPS.

For 5GSPS, you may check ADCs that supports higher sampling rate like AD9207 or AD9213

Best regards,
Peevee

Partner Forums

Partner Libraries

Products Mentioned

Associated Drivers

Sample Rate about AD9689