According to the AD9689 datasheet description, the AD9689 can provide a total clock fine delay of 363.2ps (Register 0x0111,0x0112),
Then suppose I let AD9689 work at 2500MHz(T=400ps) and delay the clock phase of CH.B 200ps behind CH.A, as shown in Figure. 93(spec page 34).
Is this equivalent to the alternating work of CH.A and CH.B? Like TIADC.
The sampling rate can reach 5Gsps?
Thanks in advance for your help.