Software Version: Vivado 2021.1
We are using AD9082-FMCA-EBZ with VCU118 at 6Gsps Sampling rate of both ADC and DAC. We used JESD204C Mode 18 for TX and JESD204C Mode 19 for RX.
The lane rate is 24.75Gbps , the FPGA_REF_CLK is 750MHz and the TX_DEV_CLK, RX_DEV_CLK is 375MHz. It is working at 6Gsps sampling rate of both DAC and ADC perfectly.
** We observed that the JRX link is unstable. Sometimes the JRX 204C link is "UNDEF" and other times the JRX 204C link is "GOOD". But most of the time the JRX 204C link is "UNDEF".
** At the JRX 204C link in the "UNDEF" case, the ADC output is working properly but the DAC output is not working.
*** In some case, we also observed that even though the JRX link is Good, we observed that the DAC IRQ status is changing. In this case, the DAC output contains more spurs with respect to message frequency.
What was the reason for this JESD204C JRX link instability?
Here I'm attaching the no_os prints of AD9082 with VCU118 :
Actual DAC output when link is Good:
In some Power ONs, the actual DAC output when Link is GOOD:
Thanks in Advance