AD9253
Recommended for New Designs
The AD9253 is a quad, 14-bit, 80 MSPS/105 MSPS/125 MSPS
analog-to-digital converter (ADC) with an on-chip sample-and-hold
circuit designed for low cost...
Datasheet
AD9253 on Analog.com
I want to use AD9253 in default setting, therefore I do not need SPI configuration. AD9253 is connected to Ultrascale+ MPSoC and I have examined the output clocks and digital output pins by using Integrated Logic Analyzer (ILA) debug core in Vivado. Then I see that the outputs do not work properly and I tried to reset the converter by using SPI port. I first tried to soft reset the converter (0x00 => 0x3C) and digital reset (0x08 => 0x03, 0x08 => 0x00). I am not using any SPI interface but giving the read/writes through FPGA/AD9253 connection. The input clock is around 16.82 MHz and SPI clock is 8.41 MHz. The results after reset are very inconsistent. Sometimes I get reasonable values on DCO,FCO and digital output pins. However, it takes a very short time and most times they do not work properly. Here is a time interval that output signals are consistent and reasonable.


If you can help about what the problem is or how can I deal with it, I appreciate it. I have some suspicions:
1) I might be trying to give SPI commands too early, before the device is powered up. However, I have tried to loop SPI commands to eliminate this probability and the results were the same.
2) Maybe I need to wait between reset commands (between 0x08 => 0x03 and 0x08 => 0x00). However I could not find such warning on datasheet.
3) I should give SPI commands through an SPI interface rather than FPGA connections. However, I checked the signals via oscilloscope and it seems there is no problem.
In addition to these, I have no idea about how to get a read from bidirectional SDIO pin on FPGA, therefore I cannot check if SPI commands have worked or not. I would also appreciate any help on this issue.
Hi carified,
Thanks for your interest in AD9253.
As per datasheet, the normal operation resumes 2.9 million sample clocks after reset.
Given that your input clock is 16.82 MHz:

For bidirectional SDIO pin for FPGA, you can refer to page 30 of the datasheet. This timing diagram will help you understand the 3-wire SPI configuration.

Thank you.
Regards,
Xavier