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AD9213 ADC JESD204B TPL Output Issue

Category: Software
Software Version: VIVADO 19.1

Hi Team,


                We are developing drivers for VCU118(Xilinx Virtex Ultrascale Plus) and HTG-FMC-AD9213(12 ADC)-AD9172(16 DAC). The HTG- AD9172 DAC with VCU118 is working properly without any issues. For developing drivers for AD9213 with VCU118, we used AD9208 as our reference design. The AD9213 ADC I'm using at 10Gsps sampling rate. The lane rate is 12.5Gbps, L=16, M=1(real ADC) , S =16 ,  F =2 , N = NP =16 ,  K =32, Full Bandwidth Mode, Subclass 1. fs = 10Gsps, FPGA_REF_CLK = lane rate / 20 = 625MHz ,  FPGA_DEV_CLK = lane rate/20 = 312.5MHz. In the HTG-AD9213 ADC , there is ADF4371 PLL which generates a 10GHz clock for ADC. The HMC7044 PLL is generating the FPGA_REF_CLK , FPGA_SYSREF and ADC_SYSREF. The SYSREF frequency = ADC Clock /2048 = 4.88MHz.The FPGA_DEV_CLK is the rx_out_clk of util_adxcvr block. 
 The JESD204B Link status is DATA, and JESD204B PLL is locked. But the  ADC output of JESD204B transport layer is noise which is fixed and not changing run to run in the chipscope. While giving external input to ADC , it won't change. The noise is fixed in the chipscope, but power on to power on the noise is changing. Can you please guide me with this. I'm stuck at this point.
Thanks in Advance
Goli Ganesh

  • Hi Goli,

    I'm sorry about the slow reply. Have you contacted HTG with your question? Do they have any FPGA reference designs for your board?

    If you would like we can send you sample FPGA code for the ADS8-V1EBZ which is the FPGA capture board used with the AD9213 evaluation board from ADI.



  • Hi  , 

      Thanks for your response. No sir, I don't have any reference design for HTG AD9213 with VCU118. I used AD9208 as our reference design. 

     Is there any JESD204B no_os sequence of AD9213 reference? I followed the stratup sequence mentioned in the data sheet of AD9213.  Any Idea about why fixed data is coming the transport layer output and why it is not changing run to run in chipscope? 

    Thanks in Advance

    Goli Ganesh

  • Hi Ganesh_Goli,

    The startup sequence in the APPLICATIONS INFORMATION section of the AD9213 datasheet is to bring up AD9213 to be ready for JESD204B link establishment, but it does not include the link establishment procedure.

    The JESD204B LINK ESTABLISHMENT section of the AD9213 datasheet contains general information on establishing the JESD link, not specific to any particular FPGA.

    We can provide you examples of the FPGA code we use on the ADI AD9213 evaluation board, but information specific to the HiTech Global board you'll need to obtain from HiTech Global.

    Thank you.


  • Hi  ,

          Thanks for your response sir. Could you please share me the FPGA code for ADI AD9213  or any reference design for ADI AD9213.

    Thanks in Advance

    Goli Ganesh

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