Software Version: VIVADO 19.1
We are developing drivers for VCU118(Xilinx Virtex Ultrascale Plus) and HTG-FMC-AD9213(12 ADC)-AD9172(16 DAC). The HTG- AD9172 DAC with VCU118 is working properly without any issues. For developing drivers for AD9213 with VCU118, we used AD9208 as our reference design. The AD9213 ADC I'm using at 10Gsps sampling rate. The lane rate is 12.5Gbps, L=16, M=1(real ADC) , S =16 , F =2 , N = NP =16 , K =32, Full Bandwidth Mode, Subclass 1. fs = 10Gsps, FPGA_REF_CLK = lane rate / 20 = 625MHz , FPGA_DEV_CLK = lane rate/20 = 312.5MHz. In the HTG-AD9213 ADC , there is ADF4371 PLL which generates a 10GHz clock for ADC. The HMC7044 PLL is generating the FPGA_REF_CLK , FPGA_SYSREF and ADC_SYSREF. The SYSREF frequency = ADC Clock /2048 = 4.88MHz.The FPGA_DEV_CLK is the rx_out_clk of util_adxcvr block.
The JESD204B Link status is DATA, and JESD204B PLL is locked. But the ADC output of JESD204B transport layer is noise which is fixed and not changing run to run in the chipscope. While giving external input to ADC , it won't change. The noise is fixed in the chipscope, but power on to power on the noise is changing. Can you please guide me with this. I'm stuck at this point.
Thanks in Advance