I'm sorry about the slow reply. Have you contacted HTG with your question? Do they have any FPGA reference designs for your board?
If you would like we can send you sample FPGA code for the ADS8-V1EBZ which is the FPGA capture board used with the AD9213 evaluation board from ADI.
Hi DougI ,
Thanks for your response. No sir, I don't have any reference design for HTG AD9213 with VCU118. I used AD9208 as our reference design.
Is there any JESD204B no_os sequence of AD9213 reference? I followed the stratup sequence mentioned in the data sheet of AD9213. Any Idea about why fixed data is coming the transport layer output and why it is not changing run to run in chipscope?
Thanks in Advance
The startup sequence in the APPLICATIONS INFORMATION section of the AD9213 datasheet is to bring up AD9213 to be ready for JESD204B link establishment, but it does not include the link establishment procedure.
The JESD204B LINK ESTABLISHMENT section of the AD9213 datasheet contains general information on establishing the JESD link, not specific to any particular FPGA.
We can provide you examples of the FPGA code we use on the ADI AD9213 evaluation board, but information specific to the HiTech Global board you'll need to obtain from HiTech Global.