AD6672
Recommended for New Designs
The AD6672 is an 11-bit intermediate receiver with sampling speeds of up to 250 MSPS. The AD6672 is designed to support communications applications, where...
Datasheet
AD6672 on Analog.com
Hi,
I am currently working to automate data collection off of the EVAL-AD6672 using the HSC-ADC-EVALCZ and the HadBoardApi.dll. I load the dll in python, can configure the FPGA using the ad9642_evalcz_0430214_0531.bin file, and am able to read back an array of data, but the data appears to just be the same number repeated over and over (when using VisualAnalog I get actual data). I believe I am missing some configuration, like potentially some SPI writes to either the FPGA or the ADC, but from the data sheet for the ADC and the source verilog files for the fpga image I cannot find anything I am missing. Can anyone share the configuration required to read data back from the EVAL-AD6672 board?
import clr #this is from pythonnet
import sys
import struct
from datetime import datetime
from ctypes import *
################################################################
## Requires 32-bit python 2.7
## Can be downloaded from: https://www.python.org/ftp/python/2.7.17/python-2.7.17.msi
## Also requires pythonnet to be installed:
### C:\Python27\python.exe -m pip install pythonnet
def main():
print( "Begining program:" )
mydllpath = r"C:\Program Files (x86)\Analog Devices\VisualAnalog"
fpgaFileName = r"C:\Program Files (x86)\Analog Devices\VisualAnalog\Hardware\HSC_ADC_EVALC\ad9642_evalcz_04302014_0531pm.bin"
# Import the .NET Assempbly
sys.path.append(mydllpath)
print( " Importing .dll" )
clr.AddReference('HadBoardApi')
from HadBoardApi import HadBoard , HadSpiParameters
# Find the board (HadBoard.BoardCount will return 0 if no boards are found)
print( " Finding boards" )
HadBoard.FindBoards()
found = HadBoard.BoardCount
if found == 0:
print( "No board found. Exiting" )
sys.exit()
# Configure the FPGA
print( " Board found :)" )
HadBoard.SelectBoard( 0 )
board = HadBoard.Board
print( " Programming FPGA" )
board.ConfigureFpga( fpgaFileName )
# Configure the ADC
params = HadSpiParameters( 1 , 0 , 1 )
board.SpiInitInterface( 1 , params )
## From the user guide, the DCO Clk Delay enable should be enabled and set to 600ps
# Need the value 0x80 | 0x05 (for 600ps delay)
# print( " Configuring ADC" )
# configValue = c_ubyte( 0x85 )
# regAddress = c_short( 0x17 )
# board.SpiWrite( regAddress , configValue )
# # write the shadow register
# configValue = c_ubyte( 0x01 )
# regAddress = c_short( 0xFF )
# board.SpiWrite( regAddress , configValue )
# Configuration we want:
###########################################################################
# Power Mode Normal - Addr: 0x08 Val: 0x00 (default)
# Duty Cycle Enabled - Addr: 0x09 Val: 0x01 (default)
# Clock Divide no delay, divide by 1 - Addr: 0x0B Val: 0x00 (default)
# Test Mode Continuous and off - Addr: 0x0D Val: 0x00 (default)
# LSB Offset Adjustment at 0 - Addr: 0x10 Val: 0x00 (default)
# Output mode bar on, 2s comp, non-inv Addr: 0x14 Val: 0x01 (default)
# Output strength 3.5mA Addr: 0x15 Val: 0x01 (default)
# Clock Phase default Addr: 0x16 Val: 0x00 (default)
# Clock output delay off Addr: 0x17 Val: 0x00 (default)
# Full Scale Adj 1.75 V p-p Addr: 0x18 Val: 0x00 (default)
# Test Patterns at 0x00 Addr: 0x19-0x20 Val: 0x00 (default)
# NSR Control 22% and disabled Addr: 0x3C Val: 0x00 (default)
# NSR Tuning at 28 Addr: 0x3E Val: 0x1C (default)
###########################################################################
# After writing any of these registers, 0x01 must be written to 0xFF to
# shift the value into the register and apply the change
# We may want to enable the NSR, but that should be the only change we would
# Want to make
# Fill FIFOs (not sure why this is necessary )
print( " Configuring FIFO" )
params = HadSpiParameters( 1 , 0 , 1 )
board.SpiInitInterface( 0 , params )
#Normal Cabture?
# configValue = c_ubyte( 0x03 )
# regAddress = c_short( 0x03 )
# board.SpiWrite( regAddress , configValue )
# FIFO size is 65536 Words (bytes?)
# ADC is 11-bit wide, so potentially FIFO is configured as only 11-bit
fifoSizeWords = 2 ** 15
Timeout = 30
board.FillFifos( fifoSizeWords , Timeout )
fifoSizeBytes = fifoSizeWords * 2
print( " Waiting on Fifo Full flag" )
fifoFull = False
#channel = c_short( 1 );
while not fifoFull:
fifoFull = board.GetFifoFullFlag( 1 )
#Capture the data from channel A (should come as unsigned char, needs to be shifted and converted)
print( " Begining data capture" )
data = HadBoard.Board.CaptureFifoBytes( fifoSizeBytes , 1 )
#data = board.CaptureFifoBytes( fifoSizeBytes , channel )
print( " Data captured. Begining conversion" )
# May need to convert to a byte array first
dataByteArray = bytearray( data )
# Convert from byte array to 16-bit words
# This assumes big=endian, 16 bit words
convertedData = []
length = len( dataByteArray )
for x in range( length / 2 ):
temp = dataByteArray[ ( x * 2 ):( x * 2 + 2) ]
tempConverted = struct.unpack('>H' , temp )
convertedData.append( tempConverted[ 0 ] )
# Write to a file
print( " Writing data to file" )
now = datetime.now()
fname = now.strftime( "Data_%m_%d_%Y_%H_%M_%S.csv" )
file = open( fname , 'w' )
for item in convertedData:
file.write( "%d\n" % item )
file.close()
print( "Data written to " + fname )
def check_version():
#Checks for 32-bit 2.7
version = sys.version
if version[ 0:3 ] != '2.7' or not ( "32 bit" in version ):
print( "Requires Python 2.7 32 bit to run. Download from:")
print( " https://www.python.org/ftp/python/2.7.17/python-2.7.17.msi" )
print( "If already installed, run using:" )
print( r" C:\Python27\python.exe main.py" )
sys.exit()
try:
import clr
except ImportError, e:
print( "Requires pythonnet to be installed" )
print( "Can be installed by running:" )
print( r" C:\Python27\python.exe -m pip install pythonnet")
if __name__ == "__main__":
check_version()
main()
Assumed answered offline. If still needing assistance, please reply or re-post.