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ad9689 sample rate in 2.7GHz can't work

Category: Datasheet/Specs
Product Number: AD9689-2600

AD9689-2600 data sheet promise max 2.7G sample rate,I use in 2.6G full bandwidth mode work well,but in 2.7G the PLL can't lock.Anyone can help with this problem? Thanks!

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[edited by: GenevaCooper at 12:25 PM (GMT -4) on 5 Jul 2022]
  • the AD9689-2600 will work at 2.7GHz sample rate. Please check the settings and try again. See figure 59 of the datasheet for more information

  • Thank you for your reply.My regster settings are below.

    {0x0000,  0x81, 1, SPI_REG_WRITE},
    {0x0200,  0x00, 1, SPI_REG_WRITE},
    {0x0201,  0x00, 1, SPI_REG_WRITE},
    {0x0571,  0x15, 1, SPI_REG_WRITE},  //jesd powerdown
    {0x0120,  0x04, 1, SPI_REG_WRITE},  //sysref contiuous ring or 0x0A fall
    {0x058B,  0x87, 1, SPI_REG_WRITE},  //scrambling en
    {0x058E, 0x01, 1, SPI_REG_WRITE},  //M=2
    {0x058C,  0x00, 1, SPI_REG_WRITE},  //F=1
    {0x058D, 0x1F, 1, SPI_REG_WRITE},  //K=20
    {0x056E,  0x00, 1, SPI_REG_WRITE},  //》=6.75G-13.5G
    {0x0571,  0x14, 1, SPI_REG_WRITE},  //jesd poweren
    {0x0701,  0x86, 1, SPI_REG_WRITE},
    {0x073B,  0x37, 1, SPI_REG_WRITE},
    //{0x056F,  0x00, 1, SPI_REG_READ},  //read pll status
    {0x1228,  0x4F, 1, SPI_REG_WRITE},
    {0x1228, 0x0F, 1, SPI_REG_WRITE},
    {0x1222,  0x00, 1, SPI_REG_WRITE},
    {0x1222,  0x04, 1, SPI_REG_WRITE},
    {0x1222, 0x00, 1, SPI_REG_WRITE},
    {0x1262,  0x08, 1, SPI_REG_WRITE},
    {0x1262,  0x00, 1, SPI_REG_WRITE},

    And zhe AD9689-2600 CLK is 2.7GHz.The SYSREF is 3.375MHz.And FPGA JESE204B PHY core set the lane rate is 13.5Gbps.Refclk and core_clk is 337.5MHz.I don't know what else I need to set?And can you tell me the reasons why PLL can't be locked ?I did not  find a detailed description of PLL related structures.

  • How are you providing the 2.7GHz clock signal? Are you sure you have enough clock amplitude at the CLK+/- pins of the AD9689?

  • I use  LMX2820 as  the  clk source.The RFOUT amplitude is theoretically about 1.3vpp.I don't have tools to actually measure it .But 2.6GHz work well.I don't think its amplitude is too small

  • How are you connecting the clock signal into the AD9689 eval board? single ended? differential? this most certainly is a clock amplitude issue where the chip isnt getting enough clock amplitude at its CLK+/- pins to generate a stable clock signal

  • Differential.Thank you for your reply.I will try to measure the quality of the clk.

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