Dear Analog team,
I am currently evaluating potential power savings by placing the ADC on my board in standby state between two successive data acquisitions. I use the AD9670 an 9674 ADCs and an FPGA to interface with these components.
After power-up, I configure the ADC registers using the SPI bus and then perform a bitslip operation to ensure the data words are "aligned" (I use only the DCO and data lines, not the FCO).
When I force the STBY input to logic high level, I observe a drop in power consumption, and the data received by the FPGA is either 0 or -1 on all 8 channels, as one can expect.
When I place the STBY input back to low level, I can see some live signal again at the FPGA level, however the data bits are no longer "aligned" in the 14-bit words.
Thus I have the following questions:
- is it expected given what I described above ? Am I 'forced' to use the FCO if I want to have correct data alignment?
- is there a low power mode which does not turn off the LVDS drivers or the DCO ?
- does the ADC expect a high-to-low transition on TX_TRIG before or after the STBY input goes back to 0?
On another topic: what is the "start code" which is mentioned in registers 0x188, 0x18B and 0x18C ? Is it a data word which is sent by the ADC after TX_TRIG ?
Thanks,
Remi
