Post Go back to editing

AD9480 Timing Diagram clarification

Category: Hardware
Product Number: AD9480


We are using the AD9480 ADC for an instrument currently under development.  I am writing the Verilog code now and I am concerned that there is an error in the data sheet.

On page 6, figure 2, the Tcp timing parameter is shown from the rising edge of CLK+ to the falling edge of DCO+.  Then is shows the DATA OUT to be nominally aligned with the falling edge of DCO+.

Is CLK+ really inverted to produce DCO+ or is this an error in the diagram?

I have scanned the document for any note about this inversion so I suspect it is an error. Obviously this is critical to reliable operation of the converter.  We need to run the converter at it's full 250Msps rate.

Thanks for your help in this matter.

  • Hello hdlguy,

    Thank you for bringing this to our attention.

    Most of our products when the data is clocked out, it should be captured at the rising edge of the DCO. This might appear to be a datasheet error but I need to verify first. Unfortunately, eval boards are already obsolete as this is a very old part so I may need some time to dig more information. For the meantime, can you try capturing data at the rising edge and see if it works?

    Thank you.



  • you need to make sure that the data is captured on the rising edge of DCO+

  • If you can check on it that would be great. It not as simple as "just clock it on the rising edge".  For the FPGA I need to write input timing constraints and then adjust the internal sampling clock with a PLL to meed that requirement. I'm pretty sure there is an error in the data sheet. Normally, an ADC like this has the rising edge of the clock aligned with the data transition.  The text seems to be saying that but the diagram contradicts that.

    I don't know if you fix data sheets for old parts like this.

  • Hi,

    Apologies for the delayed response. 

    The team reviewed that the Tcpd specifications in the datasheet table should be followed for good operation. The data capture should be done on the rising edge of the CLK+ to the rising edge of the DCO+. There has been a misrepresentation of these values in the timing diagram thus, it will be corrected in our next datasheet revision. Please see below figure for the corrected diagram.