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AD9864 settling time

Category: Hardware
Product Number: ad9864

It appears possible to pipeline readings through the AD9864 signal chain,  the next symbol can be presented to the input a couple of frames before the present reading starts to change as a result. From tests it appears to take around 11 frame periods to settle to the new value.  I am not au fait with digital filters,  is there a way of determining the minimum number of frames per symbol assuming instantaneous input change and qualifying settling to (say) 3lsb?.  Perhaps this is not documented because it is a standard formula for the filter chain, tabulated somewhere? (if so where?).  

Is there an Analog Devices simulation package one should use to explore this?, it seems odd that it is not (AFAICT) included in the data sheet.



  • Hello,

    The device was released nearly 20 years ago and no sample accurate (relative to ADC clock) model exists.  The group delay is dominated by the last stage decimation FIR filter (# of taps) and the fixed delay associated with the SSI port.  The delay from the FIR filter is 3 samples while the SSI port contributes a 4 sample delay.   While the pipeline delay of the ADC is 9 ADC clock cycles.......this is a fraction of a delay relative to the output data rate (i.e. 0.15 output clocks for Dec-by-60).  The best answer we can provide is that it the group delay will be between 7-8 clock cycles (relative to output IQ rate).

  • Thanks,   
    so the IQ output values will not start to change in response to a step input change until at least 4 IQ conversions, and the output should stabilize to the new value within 11 or 12 conversions after the input step.  So in principle one could get a valid symbol every 8th framed IQ conversion pair.
    The chip is 20 years old - is there obsolescence in the offing?, is there a suggested more modern part that I have overlooked?.