Dear Community members,
We are going to use AD9123 with Xilinx FPGA.
The ADC sampling clock frequency is 8GHz.
The following are link configuration parameters
LR=10Gbps, L=12, M=1, F=1, S=8, HD=1, N=12, N'=12, CS=0, K=32
In this case samples will be shared between lanes.
I would like to know how a frame is assembled on the ADC but I couldn't find it on the data sheet.
Please help me find the information.
Looking for something like the attached picture.
Any help and guidelines would be grateful.