The AD9213 datasheet (Rev. A), Page 73 implies that the Instruction Phase contains data bits to control the word length of the transaction as it states:
"In addition to word length, the instruction phase determines whether the serial frame is a read or write operation..."
This would be consistent with application note AN-877 (Rev. B - Interfacing High Speed ADCs via SPI), page 5 that shows 2 bits used (W0, W1) within the instruction header to define the word length when streaming / stalling the CSB. A diagram (Figure 5) shows how this can be utilised.
The AD9213 datasheet states it supports stalling on page 73:
"The CSB can stall high between bytes to allow additional external timing"
It is unclear however, when using the stalling feature of the CSB between bytes on the AD9213, how the device knows if the transaction has finished - unless it supports the W0, W1 word length feature as described in AN-877.
Therefore my questions are:
- Does the AD9213 support stalling of the CSB exactly as shown in Figure 5 of AN-877?
- If so can you confirm it uses 2 bits of the Instruction Header within the Instruction Phase of the SPI message as word length (i.e. as per AN-877)?
- If it doesn't use bits in the instruction header to define word length, when stalling between bytes - how does the AD9213 determine the end of a stream either reading/writing because the device by default auto-increments its address register?