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AD9213 test mode - loss of link

Hi,

I'm evaluating an AD9213, and I'm trying to look at the sample test data. When I set up the ADC to transmit the "alternating checkboard" pattern (0x5555, 0xAAAA), or the "on-off" pattern (0x0000, 0xFFFF), everything works fine. However, when I set the test mode to "ramp," a "PN" sequence, or any other test mode, the link fails after a second or so. Any idea what might be causing this? I'm stumped because some of the test patterns work perfectly, and others don't work at all...

Thank you!

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  • Hi bmitchell2407,

    Thank you for your interest in AD9213. I apologize for the slow reply.

    I've used the ramp and PN tests and I do not recall losing the link. Next time I'm in the lab I'll try it again.

    Are you using the ADI evaluation board along with the ADS8-V1EBZ FPGA board?

    Thank you.

    Doug

  • Hi, Doug, thanks for getting back with me. I'm using a hi-tech global HTG-12ADC-16DAC FMC board with a Stratix 10 SX development board. I'm using Altera's Jesd204B cores - 2x 8-lane cores for the ADC. It looks like with this setup I lose the link with the RAMP/PN test sample data intermittently. I have the link set up as subclass 1, with the multi-chip synchronization (sysref averaging) setup on the ADC. When the link is lost, the receiver recovers it and continues, but it doesn't seem super-stable. I'm curious about what might be different between the test modes, other than the data itself.

    I am running the ADC with a 8Gsps sample rate, 16-channel, 10Gbps line rate. I think I need to try to get ahold of an ADI evaluation board and see if it works better.

  • Hi bmitchell2407,

    I tried the ramp and PN9 pattern on my bench, at 8Gsps, 16 lanes, 10Gbps lane rate. I was not setup for subclass1 though. I did not see anything unusual and was able to run and capture continuously using ACE software.

    This was with the AD9213-10GEBZ and ADS8-V1EBZ hardware.

    I don't know what else I can tell you at this point, other than that I believe that the ramp and PN9 test modes are working fine as far as I can tell.

    I hope you can get past your issue and continue with your project.

    Doug

  • Hii  ,

      I'm also using HTG-12ADC-16DAC FMC board with VCU118. In HTG-12ADC (AD9213), HMC7044 does not generate ADC clock, but only generates ADC_SYSREF. The clock for AD9213 is produced by ADF7431, which is initialized by HMC7044. I want to know how ADF7431 can be initialized with respect to HMC7044 in Xilinx SDK. Any reference would be helpful.

    with regards

    Goli Ganesh

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