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Missing User patterns data in AD9213

Hi,

I'm attempting to test the AD9213 with different test modes. The AD9213 is on the HTG board (part number: HTG-FMC-12ADC-16DAC) and connects to the VCU128 FPGA kit through the FMC connector. On FPGA, I used JESD204 IP from Xilinx to communicate with AD9213 through multiple gigabit lanes.

The relevant parameters and corresponding register settings are shown below where applicable.

  1. L = 16 (# of lanes)
    1. AD9213 - JTX_SCR_L_CFG (0x0520) = 0x000F
    2. JESD204 Core – Lanes in Use (0x0028) = 0xFF
  2. F = 2 (octets per frame)
    1. AD9213 - JTX_F_CFG (0x0521) = 0x0001
    2. JESD204 Core – Octets per Frame (0x0020) = 0x0001
  3. K = 32 (frames per multiframe)
    1. AD9213 - JTX_K_CFG (0x0522) = 0x001F
    2. JESD204 Core – Frames per Multiframe (0x0024) = 0x001F
  4. N = 16 (converter resolution)
    1. AD9213 - JTX_CS_N_CFG (0x0524) = 0x000F
  5. N’ = 16 (bits per sample)
    1. AD9213 - JTX_SCV_NP_CFG = (0x0525) = 0x000F
  6. M = 1 (# of converters)
    1. AD9213 - JTX_M_CFG (0x0523) = 0x0000
  7. CS = 0 (# of control bits)
    1. AD9213 - JTX_CS_N_CFG (0x0524) = 0x000B
  8. Subclass: 0
    1. AD9213 - JTX_SCV_NP_CFG (0x0525) = 0x000F
  9. Scrambling: Disabled
    1. AD9213 - JTX_SCR_L_CFG (0x0520) = 0x000F
    2. JESD204 Core – Device Subclass (0x002C) = 0x0000
  10. Test Mode: I used 3 different test modes
    1. Alternating checker board (0x5555-->0xAAAA-->0x5555 ...) 
      1. AD9213 - JTX_LINK_CTRL1 (0x503)=0x0014
      2. AD9213 - JTX_LINK_CTRL3 (0x505)=0x0001
    2. Continuous user test (user-pattern 1 to 4, then repeat)
      1. AD9213 - JTX_LINK_CTRL1 (0x503)=0x0014
      2. AD9213 - JTX_LINK_CTRL3 (0x505)=0x000E
      3. My data were:
        1. UP1 = 0x3B1B
        2. UP2 = 0x7654
        3. UP3 = 0x3B1B
        4. UP4 = 0xFEDC
    3. Single user test (user-pattern 1 to 4, then zero)
      1. AD9213 - JTX_LINK_CTRL1 (0x503)=0x0014
      2. AD9213 - JTX_LINK_CTRL3 (0x505)=0x000F
        1. My data were:
          1. UP1 = 0x3B1B
          2. UP2 = 0x7654
          3. UP3 = 0x3B1B
          4. UP4 = 0xFEDC
    4. Physical Parameters:
      1. AD9213 Sampling clock = 10GHz
      2. JESD204 ref clock = 312.5MHz
      3. JESD204 core clock = 312.5MHz
      4. Lane rate = 12.5 Gbps
      5. Clocking and JESD204 configuration matches guidelines here: https://www.xilinx.com/support/answers/71575.html

    The problem is that when I tested the AD9213 in single-user test mode, after the ILAS phase I only got zeros (data = 0x0000) which means that I somehow failed to capture user-pattern 1 to 4 at the beginning of the data phase.

    Below are the pictures of three different test modes that I used.

    1. Picture 1 - Alternating checkerboard: as you can see that after the last character of the ILAS phase which is "7C" (/A/ character), the captured data are "5555" and then "AAAA" which are quite correct.

    2. Picture 2 - Continuous user test: After the last character of the ILAS phase which is "7C" (/A/ character), the captured data are "3B1B" (UP1) and then "7654" (UP2), UP3, UP4 and so on which are also quite correct.

    3. Picture 3 - Single-user test: After the last character of the ILAS phase which is "7C" (/A/ character), the captured data are "0000" instead of UP1 to 4 (0x3B1B -->0x7654-->...) which are not correct.

    So I did not know if I had just missed the data (UP1 to UP4) from the AD9213 or the AD9213 did not send that data (UP1 to UP4) to FPGA through the JESD204 interface.

    Any insights on what may be wrong or how to troubleshoot this problem would be extremely helpful. Thanks in advance.

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