AD9284 LVDS common mode voltage problem

Hi amelie, 

Thank you for your interest in AD9284.

The typical behavior of the LVDS output would be around 1.15-1.35V for output offset voltage and 290-400mV for differential output voltage. Kindly check if the the pin supplies AVDD and DRVDD are both 1.8V and the supply current IDRVDD is around 51mA. Also, can I ask what are the peak-to-peak values of the input signal and the differential signal after the ADC driver?

It seems that there is a mismatch in the input span of the ADC which is 1.2Vpp and the output span of your ADC driver is 2Vpp. 

I recommend the following solutions:

• To check the differential signal of the ADC driver.
• To recalculate the feedback resistor of the ADC driver to match the 1.2Vpp of the AD9284 if you have an input signal of 2Vpp, or

• To follow the configuration of the AD9284 data sheet specifically the Figure 19 for input signal of 1.2Vpp.

Best regards,

Xavier

I checked all power supplies, everything is nominal as it should be. I know it seems there is a mismatch but ADC driver is designed around 50ohm input impedance, so the gain must be set to 2. Input signal gets divided on the input so 1Vpp input is 500mVpp on the input of the ADC driver. As you can see from the picture below purple trace shows differential signal on the input of AD9284, it is 1Vpp.

On all 4 AD9284 ICs analog common mode voltage VCM is 1.68V and not around 1.4V as specified in datasheet, although there isnt any specification of VCM tolerance and drift in the datasheet.

I dont know why there wouldnt be any common mode voltage on all 36 LVDS pairs, because analog system for driving the analog inputs is working as I designed it to be honest, and all power supllies are nominal. There isnt much else on the board except 250MHz clocking subsystem, which also provides correct clock to AD9284s. I can only assume that AD9284 detects there isnt any receiver or termination connected so it tri-states or pulls to ground al LVDS pins. I didnt create FPGA design to verify this yet so Im asking here if that is maybe the problem.

Thanks

Hi amelie,

Thanks for your response. With regards to FPGA, it will constitute as a problem to the LVDS output if it is not configured properly.

I suggest the following recommendations:

• If possible, disconnect the FPGA first from the LVDS and probe the LVDS outputs to check if it functions properly using DMM continuity test for possibility of short.
• to check the SPI registers if the output enable, specifically the bit 4 of address 0x14, is set to 0. 

I also included the user guide of the AD9284 evaluation board for your schematic reference. AD9284-250EBZ_UG-178 (Rev. A) (analog.com) Moreover, if you have other prototype boards, please check if it encounter the same problem. Sharing with you below are snippets from our evaluation board. Hope this will help.

Regards,

Xavier

Hi, my schematic agrees with eval schematic so that is ok, bare AD9284 without any fpga connected shows voltage of 300mV DC at all LVDS outputs.

But maybe you have found a solution, register 0x14 seems to initialize to 0x00 at reset, and that means that outputs are disabled because enable need to be at 1, is that correct?  I thought that default reset configuration is ok for my use case, but it seems that I missed bit4 in 0x14 register, if bit4 needs to be 1, that is most certainly the problem. I need just to verify this.

Thanks