I am working through a design where that output of a RF detector circuit with a differential output is to be sampled by the AD9201. It is not my design, but I am responsible for figuring out what is not working correctly.
The output of the detector is converted to differential using a couple of operational amplifiers. On the output of each amplifier is a series 150 ohm resistor at about 6.33mA resulting in each output going from 0 to 1V and 0 to -1V.
The differential signals are filtered (6 MHz LPF) and then scaled by an AD8137. The output of the op amp ranges from 1.5V to 2.5V (1V differential).
The next step is using the AD9201 to sample the differential signal.
Here is where I think I am having issues.The designer is using two external resistors to set the Vref voltage to 2.43V with a span of 2.43V.
What I need validation on is the datasheet specifies the ANALOG INPUT voltage range to be from -0.5 to AVDD/2 (5V/2 = 2.5V). The FPGA designer says that he is only seeing 4 or 5 bits ever toggle. So, is this the source of the error. (Our Systems guy has no hardware for me to test my theory but we are going through a board respin and have the chance to fix and verify on the next prototypes.)
Thanks in advance!
