AD9656 Timing & Data Mapping

Question

Hi, 
 
 I am using my own FPGA board and AD9656 PCB to verify the JESD204B protocol. But I can't get any data with my current configuration. So I have some questions about this AD9656 DATA output config. 
 
 (1) By default, the AD9656 would output data without any configuration, is that right? 
 (2)The default configuration is: M=4, Lane=1, if ADC clk = 100MHz, then, data output rate is 4Gbps, is that right? 
 (3)The default configuration timing is like below, I want to know where is location of the LSB part, are they following at next clk cycle by the same pattern? 
 
 (4)If I use quick config, Setting 0x5E with value 0x44, which mean M=4, Lane=4, clk=100MHz, then what is the data output rate? Is it still 4Gbps? 
 (5) With qucik config M=4, Lane=4, How does the ADC data map to the JESD204B Lane? Is the picture mapping below correct?

DougI · Accepted Answer

Hi eleday, 
 I've requested that the sample FPGA code be emailed to you. It should be sent early next week. 
 I'm not an expert on JESD, but here is some basic information. 
 SYSREF frequency is equal to the LMFC frequency, or is a subharmonic of it. 
 LMFC frequency is the Frame Clock frequency divided by the JESD204B parameter K, where K is the number of frames per multiframe (configurable on the AD9656). 
 The Frame Clock frequency is the ADC sample clock frequency divided by the JESD204B parameter S, where S is the number of samples transmitted/single converter/frame cycle (AD9656 value = 1). So for AD9656, the Frame Clock frequency is the same as the ADC sampling frequency. 
 The AD9656 SYNCINB signal is the SYNC~ signal defined in the JESD204B standard document. This is a handshaking signal the JESD receiver uses to initiate synchronization. 
 I suggest you look at some JESD204B reference material for more information. 
 Thanks, 
 Doug)

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AD9656 Timing & Data Mapping