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AD9656 Timing & Data Mapping


   I am using my own FPGA board and AD9656 PCB to verify the JESD204B protocol.  But I can't get any data with my current configuration. So I have some questions about this AD9656 DATA output config.

(1) By default, the AD9656 would output data without any configuration, is that right?  

(2)The default configuration is: M=4, Lane=1, if ADC clk = 100MHz, then, data output rate is 4Gbps, is that right?

(3)The default configuration timing is like below, I want to know where is location of  the LSB part, are they following at next clk cycle by the same pattern?

(4)If I use quick config, Setting 0x5E with value 0x44, which mean M=4, Lane=4,  clk=100MHz, then what is the data output rate? Is it still 4Gbps?

(5) With qucik config M=4, Lane=4, How does the ADC data map to the JESD204B Lane? Is the picture mapping below correct?