Post Go back to editing

AD9656 Timing & Data Mapping


   I am using my own FPGA board and AD9656 PCB to verify the JESD204B protocol.  But I can't get any data with my current configuration. So I have some questions about this AD9656 DATA output config.

(1) By default, the AD9656 would output data without any configuration, is that right?  

(2)The default configuration is: M=4, Lane=1, if ADC clk = 100MHz, then, data output rate is 4Gbps, is that right?

(3)The default configuration timing is like below, I want to know where is location of  the LSB part, are they following at next clk cycle by the same pattern?

(4)If I use quick config, Setting 0x5E with value 0x44, which mean M=4, Lane=4,  clk=100MHz, then what is the data output rate? Is it still 4Gbps?

(5) With qucik config M=4, Lane=4, How does the ADC data map to the JESD204B Lane? Is the picture mapping below correct?

  • Hi eleday,

    Thank you for your interest in AD9656. Here are some responses to your questions.

    1. Yes, AD9656 has a valid default configuration but there are JESD204B link bring-up steps that are needed to establish the link. The AD9656 datasheet has a summary of these steps. The complete description is in the JESD204B standard document which is available from JEDEC.
    2. For M=4, Lane=1, if ADC clk = 100MHz, then, output bit rate is 8Gbps. If you change to L = 2, then the output bitrate would be 4Gbps.
    3. The data comes out MSB first, so the LSB (the one least significant bit) for each converter and each sample, is the last data bit before the MSB of the next word. Please note that the screenshot conceptual diagram is of encoded data so the 16 data bits from the ADC would not be obvious.
    4. With M=4, L=4 and the clock frequency is 100MHz, then the output bitrate is 2Gbps. When you double the number of lanes, the output bitrate is halved.
    5. I agree with your mapping picture, where "MSB" represents the 8 MSBs and "LSB" represents the 8 LSBs.

    We can provide sample FPGA capture code for AD9656 if you would like to see it. It does not include the JESD204B IP though. You would need to get that from Xilinx.

    Thank you.


  • Hi Dougl:

       Could you send me the sample FPGA capture code for AD9656? thanks, 

       my email:

  • Hi Jerry.X,

    Thanks for your interest in AD9656. I'll request that the sample FPGA code be sent to you.


Reply Children
No Data