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When using AC-LVPECL as the sampling clock for AD9652


I want to apply a AC-LVPECL clock to the clock input of AD9652.

I am wondering how can I optimize it in hardware. 

The specifications of applied clock are as below.

Output voltage swing (VOH-VOL)

MIN     TYP     MAX

620      780      900 (mV)


2xVOD (Vpp)

Output common mode 

MIN     TYP     MAX

300                 700 (mV)

Figure 62 of the AD9652 datasheet shows how the PECL driver is connected. But it seems to be for DC coupled LVPECL. 

Can I design like Figure 62 for the clock input of AD9652 regardless of AC or DC coupled?

Please help me optimize that connection.

Added comment
[edited by: seung-gon at 8:22 PM (GMT -5) on 24 Jan 2022]