Hi,

For the EVAL-AD9213 Board I can see from the schematic that the Differential Data Output Lanes are as follows:

Lane 0: Normal

Lane 1: Normal

Lane 2: Inverted

Lane 3: Inverted

Lane 4: Normal

Lane 5: Inverted

Lane 6: Normal

Lane 7: Inverted

Lane 8: Normal

Lane 9: Normal

Lane 10: Normal

Lane 11: Normal

Lane 12: Normal

Lane 13: Normal

Lane 14: Normal

Lane 15: Normal

I am working to interface with an Intel Stratix 10 TX Transceiver Eval board and utilize only the first 8 Lanes at a relatively low speed of 3.0 GSPS.

In order to correct the Signal polarity, I would expect to do the following.

1.  Enable Data Inversion by setting register 0x622 to 0x04

2.  Write register 0x5ea to 0xac to Invert Lanes 2,3,5,7.

I am monitoring the output of the Intel JESD 204B IP via signal tap, and I have tried this and I have not seen any effect on the datastream.  

Are there any additional settings in the register map that need to be set?  Is there a specific order in the initialization of when these settings need to be set?

Thank you,

Will