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AD9213 NCO multi-chip synchronization

We have a proprietary board with two ADCs AD9213.
Multi-chip synchronization (MCS) is used to make them aligned.
This procedure uses Averaged SYSREF mode.
Synchronization works OK in full bandwidth (FBW) mode.

Now we are trying to use the chips in DDC mode. One-by-one, they function properly.
Now we want to synchronize them.
For DDC, this synchronization includes two parts:
Part1. General sync (the same as MCS in FBW mode)
Part2. NCOs sync
By our observations, the Part1 works also OK for DDC (the same MCS procedure with Averaged SYSREF is used).
The Part2 was not implemented initially, so after each re-init and re-sync,
it was random phase shift between sine waves at DDC outputs (the same sine signal is applied to both inputs).

Now we implemented Part2 (NCO sync) procedure according to the spec.
We use the option without TRIG_x signal:
Reg 0x600, Bit 0 = 1 (DDC_SYNC_EN)
Reg 0x600, Bit 1 = 1 (DDC_SYNC_NEXT)
Reg 0x600, Bit 7 = 0 (DDC_TRIG_NCO_RESET_EN)
and also Averaged SYSREF mode.

Looks like there is a problem with this Part2 (NCO sync) procedure.
Still, after re-init and re-sync, there is random phase shift at DDC outputs.

Because of all above, the following questions have arisen (about startup sync procedure):
Q1. Can Part2 (NCOs sync) be performed with Averaged SYSREF?
Q2. Should Part1 (General sync) and Part2 (NCOs sync) be run simultaneously (on the same set of periodic SYSREF pulses) or one-by-one?
Q3. Is there any indicator that NCO sync procedure is done successfully? There is the r/o register 0x601 DDC_SYNC_STATUS, bit 0 DDC_SYNC_EN_CLEAR.
       Can it be used as such an indicator?

Would appreciate your help.
Thank you,

  • Hi Dmytro,

    Happy New Year.

    Have you made any progress? Here is some information regarding your questions.

    Q1 Yes, NCO synchronization can be performed with Averaged SYSREF. Setup DDC_SYNC_EN, DDC_SYNC_NEXT and DDC_TRIG_NCO_RESET_EN before SYSREF is applied and before MCS lock is achieved.

    Q2 There is no need to synchronize first in Full Bandwidth Mode before synchronizing when using the DDC, if that is the question.

    Q3 Yes, I believe that DDC_SYNC_EN_CLEAR can be used as an indicator that NCO synchronization was done. I'm getting confirmation on if DDC_SYNC_EN_CLEAR = 1 means that the action has been completed, or if it means completion and successful synchronization.



  • Doug, thank you very much for the answers.

    Q1. I tried to test your suggestion. I only had to change in our procedure DDC_TRIG_NCO_RESET_EN (Reg0x600[7]) = 1 instead of 0. Unfortunately, it seems NOT to work - still the signals at DDC outputs have random phases.

    I thought that DDC_TRIG_NCO_RESET_EN=1 makes the chip use TRIG_x signal (see Table 10) (to remind, it is NOT used in our case)

    Q2. I didn't mean FBW mode first. In our case, FBW mode uses 12 JESD lanes while DDC (few different modes) use 8,4,2 or 1 lanes. For changing number of lanes, we do SoftReset+full chip initialization. During this initialization, already in DDC mode, general MCS procedure (what I call Part1) is done. Currently, we are trying NCO sync simultaneously with MCS procedure (averaged SYSREF) (and it does not work, see Q1).



  • Hi Dmytro,

    I'm sorry for the slow response.

    I'm sorry for my mistake regarding DDC_TRIG_NCO_RESET_EN.

    • You are getting MCS lock after the bits are set, correct (Register 0x151E, Bit 1 = 1)?
    • What do you see when you read DDC_SYNC_EN_CLEAR?

    Could you try NCO test mode, and see what this produces? If you set Register 0x630 Bits[4:3] = 11, this puts the NCO into test mode. The NCO will produce a close-to-full-scale tone at the NCO frequency. Do see these tones in alignment after resetting the NCOs?



  • Hi Doug,

    Now I am sorry for the delay, notification about your comment was by some reason lost.

    The sequence at our current MCS procedure (with simultaneous attempt of NCO sync) is the following:

    • Setup everything
    • Read DDC_SYNC_EN_CLEAR from both chips. They read 0s
    • Turn on periodic SYSREF
    • Wait for MCS locks Reg0x151e[1] =1
      • They become locked within ~30 ms
    • Turn off periodic SYSREF
    • Read DDC_SYNC_EN_CLEAR from both chips. They now read 1s

    We will try NCO test mode Reg0x630[3:2]=11 at our earliest convenience.

    Thank you,


  • Hi Doug,

    Some results about NCO test mode:

    • If to dynamically set Reg0x630[3:2] to 11 (after init is finished) - nothing changed (as if test mode is not turned on)
    • If to insert this setting into init procedure (instead of 00 (Variable IF mode)), then test mode seems to really activate. Observations with it:
      • At high NCO frequencies (outside of resulting span), output signal is close to 0 (this seems to be OK)
      • At low NCO frequencies (within resulting span), signals look as full-scale sine waves. Phase shift between them is random and changes after each re-init (wanted to upload image, but the editor does not allow it by some reason)



    • Doug,

      Some more news on NCO sync.

      We decided to try sampled SYSREF mode (instead of averaged), and got NCOs synchronized!

      It is confirmed to work both in NCO test mode and in normal operation (Variable IF) with input signal split from one generator. The phase shift between channels now is constant (180 degrees in NCO test mode and some small value in normal mode).

      Though, we are not sure in stability of operation with sampled SYSREF. Currently, after few repetitions of init (~5 times), I always get stable results. But due to very small SYSREF receive window (100 ps, we work at 10 GSPS), it probably won't be guaranteed on other boards and in wider temperature range.

      So, we need to continue trying to make averaged SYSREF mode work. Would appreciate your help in this.



    • Hi Dmytro,

      Thank you for sharing your results. I will take this information to the design group and get find out more about what is going on.

      Thank you.


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