We have a proprietary board with two ADCs AD9213.
Multi-chip synchronization (MCS) is used to make them aligned.
This procedure uses Averaged SYSREF mode.
Synchronization works OK in full bandwidth (FBW) mode.
Now we are trying to use the chips in DDC mode. One-by-one, they function properly.
Now we want to synchronize them.
For DDC, this synchronization includes two parts:
Part1. General sync (the same as MCS in FBW mode)
Part2. NCOs sync
By our observations, the Part1 works also OK for DDC (the same MCS procedure with Averaged SYSREF is used).
The Part2 was not implemented initially, so after each re-init and re-sync,
it was random phase shift between sine waves at DDC outputs (the same sine signal is applied to both inputs).
Now we implemented Part2 (NCO sync) procedure according to the spec.
We use the option without TRIG_x signal:
Reg 0x600, Bit 0 = 1 (DDC_SYNC_EN)
Reg 0x600, Bit 1 = 1 (DDC_SYNC_NEXT)
Reg 0x600, Bit 7 = 0 (DDC_TRIG_NCO_RESET_EN)
and also Averaged SYSREF mode.
Looks like there is a problem with this Part2 (NCO sync) procedure.
Still, after re-init and re-sync, there is random phase shift at DDC outputs.
Because of all above, the following questions have arisen (about startup sync procedure):
Q1. Can Part2 (NCOs sync) be performed with Averaged SYSREF?
Q2. Should Part1 (General sync) and Part2 (NCOs sync) be run simultaneously (on the same set of periodic SYSREF pulses) or one-by-one?
Q3. Is there any indicator that NCO sync procedure is done successfully? There is the r/o register 0x601 DDC_SYNC_STATUS, bit 0 DDC_SYNC_EN_CLEAR.
Can it be used as such an indicator?
Would appreciate your help.