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AD9628 sometimes stuck after power-up

This is not really a question but an observation. I have tested several hundred of our own SDR boards featuring an AD9628 and a Xilinx Zynq SoC. The AD9628 AVDD and DRVDD supplies are powered by the same 1.8V rail as there are no limitations in the datasheet with respect to a power-up sequence or timing. The PDWN and SPI pins are connected to and controlled by the SoC.

I found that in a small percentage (~ 1 %, maybe less, depending on component tolerances, temperature, etc.) of power-ups, the ADC would not start operating (no DCOA/DCOB and DnA/DnB) even though the registers are accessible and the initialization sequence (PWDN = 1 -> 0, soft reset, digital reset) is executed. Even if I repeat the initialization sequence several times, the only way to resolve the situation is to power-cycle the board.

I found some related topics / links where users have observed a similar behaviour:

https://ez.analog.com/data_converters/high-speed_adcs/f/q-a/21463/ad9628-freeze-during-initialize

https://ez.analog.com/data_converters/high-speed_adcs/f/q-a/21866/ad9628-power-up-sequence

https://engineerzone36.rssing.com/chan-15421706/all_p321.html

https://indico.in2p3.fr/event/18210/sessions/11265/attachments/51619/66397/adc_power_supply.pdf

Particularly the last link was helpful in reproducing and mitigating the issue. Because I am not able to control AVDD separately on our boards, I placed a large capacitor after the ferrite bead that is used to filter the AVDD supply. This results in a slight delay (several us) on power-up and hence no more issues with ADCs being stuck.

Of course, a separate AVDD supply that can be sequenced would be the ideal solution. Maybe this helps other people that are facing the same problem.

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