BRAM fifo enable signal & data order showed in VA.

Hello,

I have a question about the FPGA program for virtex6- based EVALEZ capture board. I am using this board to work with AD9681 to process 8 channel ADC signal.  

I modify the reference code to control the BRAM enable signal as I want. 

data format to write in BRAM follow the default BRAM_wr_data : 128 bit (D2,C2,B2,A2,D1,C1,B1,A1) (capture mode: octal with BRAM_WORD_NUM = 8)

every time my BRAM_en signal "up" (random) : Write it into the BRAM. 

The problem I would like to ask is : If I do it, whether or not the order of data show in VA (8 channel) affected by my modification.

Thank you very much!

HOANG