LTC2157-14, Clock Duty Cycle Stabilizer

Hi,

I have a question.

 https://www.analog.com/media/en/technical-documentation/data-sheets/21576514fb.pdf , page 5,  "TIMING CHARACTERISTICS", Note8

"Note 8: Guaranteed by design, not subject to test." is described.

In the condition of  "Clock Duty Cycle Stabilizer OFF ", the minimun time of "ENC Low Time" and "ENC High Time" are 1.9 ns.

In the condition of 250Msps, Duty Cycle for ENC+/- pins are defined 47.5%-52.5%.

In the condition of 250Msps, Duty Cycle for ENC+/-  is 45%~55% in our design.

Our design requires "Clock Duty Cycle Stabilizer". 

Does The "Clock Duty Cycle Stabilizer" work?

Is the above-mentioned understanding right?

 

Best Regards,

A.Wakebe/TED