HMC7044_Sysref in Pulsed mode with DC Coupled LVDS termination

Hi!

I'm trying to use Sysref in pulse generator Mode (8pulses) 0x005A -> 04, with sysref channels in dynamic mode 0x00D2 -> DD. but i observe the sysref line is getting toggled (Runt pulses) when it is in off state(Pulse generator in done state 0x091 -> 02). similar to querry: https://ez.analog.com/clock_and_timing/f/q-a/19735/hmc7044-pulse-generator-request/171758#171758.

I have connected Sysref lines to FPGA in LVDS DC Coupled mode(Internal 100 om termination enabled in FPGA).

Is there any termination needed to keep the sysref in a fixed logic state when not generating pulses as per request ?

Thanks in advance,

Deva

  • Hi Deva,

    Output driver is not able to keep the idle voltage level at Logic-0 when it is working in LVDS n-pulse mode.

    The workaround for that is to use LVPECL output driver. But, in most of the cases, the down-stream device (ADC/DAC/FPGA) is not compatible with LVPECL level. So, there is a level translation network required to convert LVPECL swing level and common mode voltage to LVDS level as below

    Kudret.