AD9695_Subclass1,N-Shot mode

Hi, Analog Team!

We have designed a customized board  with AD9695(3Nos) & HMC7044 and are facing problems while trying to perform multichip NCO synchronization.

First of all, It would be greatly helpful if you could clarify some of the below doubts,

1)while trying to follow Figure 133. SYSREF± Capture Scenarios and Multichip Synchronization, we are un-able to find the “JESD204B LMFC Alignment Required?” Control Register. Can you please specify the register used for the marked function as shown below,

2)we tried to perform NCO Multichip Synchronization mentioned in Page52 of data sheet and configured
0x0040-> 31 & 0x0041->80 (Chip FD_B/GPIO_B0 set as MNTO)  in ADC1
0x0040-> 31 & 0x0041->90 (Chip FD_B/GPIO_B0 set as SNTI). In ADC2.
As all GPIO are connected to FPGA in our module, we planned to relay the MNTO Signal From ADC1 to SNTI of ADC2, But observed that the MNTO never Went High. Is there something we missed out for using  Master/Slave Synchronization Triggering mechanism?

3)In NCO Multi chip synchronization Figure 104, It is shown that a common signal is routed to all ADC, Can you please share the Function/pin details for this signal?

We are operating in subclass1, Sysref continuous mode, we are able to perform multi NCO synchronization by writing NCO synchronization bit (300 → 3) in all ADC's. And phase matching works fine. But due to continuous sysref, we are observing sysref spurs in ADC output at ~ -49dBc, which is un-suitable for our application. Hence we opted for N-shot mode. And are observing the following issues,

we configured HMC7044 in pulse generator mode(8pulses) & kept sysref channels in dynamic mode and AD9695 in subclass1(0x0590 → 2F), N-shot(0x0120 → 4) and NCO next sysref sync(0x0300 → 3).  we then  perform Jesd Lane bonding by asserting sync and ILA sequence gets completed & we are able to log data. At this instance, verified that the ADC's are waiting for Sysref Pulses(read 0x0120 → 4). we then give pulse generator request to HMC7044, and then read 0x0120 → 0 & 0x0300 → 2 which indicates sysref is received, but observed ADC channel bonding gets disrupted. Why ? Is there any sequence to achieve synchronization with N-shot mode.

We also observed that, on providing Sysref Pulse(8), in ADC2 Both Sysref N-shot(0x0120) + NCO sync(0x0300) gets cleared while in ADC & ADC3, only Sysref N-shot(0x0120) is getting cleared. Is there any timing that needs to be met for performing both with a single Pulse request?

Kindly guide us achieve Multi Chip NCO synchronization with AD9695 in N-shot mode.

Thanks in advance,

  • Hi,

    Answer to Q1:

    The box highlighted in yellow in the figure is a decision box. It is asking if the user requires LMFC alignment in their system. If LMFC alignment is required, proceed to the 'yes' branch. Otherwise, proceed to the 'no' branch.

    Answer to Q2:

    Please follow the sequence bellow to configure MNTO/SNTI.

    1) Configure initial state (asynchronous events) :
    a) In Master, enable MNTO on GPIO output pin.
    b) In Master, enable SNTI on GPIO input pin. (Optional)
    c) In Slave(s), enable SNTI on GPIO input pin.
    d) Configure Slave(s) in SYSREF “Next Trigger” mode. (Sysref Control reg 0x120 mode select = “11”)
    e) In Clock Generator, enable periodic SYSREF to all devices. (SYSREF period must be > MNTO to SNTI board propagation time + master/slave I/O propagation times.)
    f) Set NCO phase accumulator update mode to “Continuous Update” Mode.(Optional)
    g) Set NCO tuning frequencies (Optional)
    h) Set NCO phase accumulator update mode to “Transfer Mode” (Optional)
    2) Configure Master in SYSREF “Next Trigger” mode. (asynchronous event) (Sysref Control reg 0x120 mode select = “11”)
    3) On next SYSREF, MNTO set high synchronously by Master. (synchronous to SYSREF)
    4) Internal NSTE driven high before next SYSREF event (synchronous to SYSREF)
    a) In Slave(s), NSTE driven by SNTI.
    b) In Master, NSTE driven by either SNTI (if configured) or MNTO (default).
    5) System Synchronization Achieved!
    a) While NSTE is high, next SYSREF synchronizes LMFCs, NCOs, and FHTs in Master and Slave(s).
    b) SYSREF “Next Trigger” mode automatically disabled in all ADC devices.
    6) Subsequent SYSREFs are ignored

    Answer to Q3:

    The common signal is device clock. It is supposed to be connected to the device clock label at the bottom of the figure.


  • Hi,

    Thanks for your Response.

    How to select LMFC alignment is required or not? Unable to find it in Register Map section. Please share the address of the control register.

    Thanks,We will try it out & come back.

    Question4("Issue" stated in post on Nov 21, 2021):
    The Sysref to all 3 ADC's are length matched, But on providing N-shot(16 synchronous pulses of 640KHz) from HMC7044, JESD Bonding gets disrupted, what could be the issue?

    Question4("Issue" stated in post on Nov 21, 2021):
    we configured Sysref N-shot(0x0120) + NCO sync(0x0300). For a single shot of sysref(16 synchronous pulses of 640KHz), i was hoping for both [LMFC alignment(0x0120 cleared) + NCO sync(0x0300 cleared)]. but it is not happening, Only LMFC gets cleared. what is the procedure to perform LMFC + NCO sync with a 1-shot SYSREF Synchronous Pulse?

    Thanks in advance,

  • Answer to Question 1:

    LMFC alignment is a system requirement (or not), It is not a single register setting. If LMFC alignment is required, proceed to the 'yes' branch. Otherwise, proceed to the 'no' branch.

    Answer to Question 3:

    You can use the SYSREF set up and hold detector registers to see if set up and hold timing is met. You can also use the SYSREF counter register to see if the ADC is receiving SYSREF signal. 

    Answer to Question 4:

    Issue from question 3 needs to be resolved before synchronization can be achieved.