AD9249 Data reconstruction issue.

Hi,

I'm using the same source code of AD9249 provided by analog devices. But I'm getting Hold and Negative Slack Issues in the bit file generation. I'm just change the drp_reference_clock to On board clock of ZC706 using Clocking Wizard (generating 100MHz) for data clock control module. In the output wave forms, the samples are missing while reconstruction. The hold slack issues are due to FCO_CLK and ISER_DDR_F0 in the iser_top.v module. I want to reconstruct the continuous signal without sample missing. 

Help me to fix these timing issues.

Thank you,

B. Mourya

  • Hi, 

    we are still waiting for the reply. Although we are doing modifications to solve the data reconstruction issue , the problem is not being solved. Kindly look in to this issue and give us a reply.

  • Hi ,

    we have run the post implementation timing simulation for the AD9249 driver code given by the analog devices. we are facing samples missing during reconstruction of the ADC data in the timing simulation also which is similar to the issue we are facing during the Hardware testing as  mentioned in the previous post. Kindly help us to solve this issue.

    Thank you,

    B.Mourya

  • Hello @AdrianC ,

    Kindly look into this issue 

  • Hi,

    Apologies for the delayed response.

    Before going to software side of things, I would like to check if you have done the following:

    1. Have you performed digital reset? This is just to ensure that the AD9249 is initialized properly.

    2. Have you verified one of the Output Test Modes? It can be found in Table 11 of the data sheet. The advantage of verifying these test pattern is to validate the communication from ADC to FPGA. You can select various test patterns and see if they are captured correctly by the FPGA.

    3. With regards to timing issue, you can try to vary the timing between DCO and Data through Register 0x16 Bits[3:0] and see if it makes capture better or worse.

    Hope this helps your issue and let me know how it goes.

    Regards,

    Meriam

  • Hello  

    Same issue here.

    We have AD9249-65EBZ board + HSC_ADC_EVALEZ board and sample code ad9249_evalez_src_04.14.20 from ADI and tried following steps.

    1. The 3MHz sinusoidal signal was fed to all 16 channels of AD9249-65EBZ and onboard default 65MHz clock was used.

    2. Sample code ad9249_evalez_src_04.14.20 was compiled and programmed onto HSC_ADC_EVALEZ. All signals were captured properly.

    3. Then a new project was created with the sampling code adopted from the sample code ad9249_evalez_src_04.14.20. But the signal could not be captured correctly.

    4. Back to step 2, performed "fix instance" onto the netlist created from sample code and copied the constrains of the level 1 register into the new project created in step 3. The new project worked properly then.

    I was wondering if the sample code ad9249_evalez_src_04.14.20 was optimized or fine-tured for the AD9249-65EBZ board. If so, how?

    Thanks

    Here are the contstrains copied into new project:

    # PlanAhead Generated physical constraints

    INST "iser_top1/iser_ddr_i0/dout_reg_1" BEL = DFF;
    INST "iser_top1/iser_ddr_i0/dout_reg_1" LOC = SLICE_X46Y102;
    INST "iser_top1/iser_ddr_i0/dout_reg_0" BEL = CFF;
    INST "iser_top1/iser_ddr_i0/dout_reg_0" LOC = SLICE_X46Y102;
    INST "iser_top2/iser_ddr_i0/dout_reg_1" BEL = BFF;
    INST "iser_top2/iser_ddr_i0/dout_reg_1" LOC = SLICE_X54Y118;
    INST "iser_top2/iser_ddr_i0/dout_reg_0" BEL = AFF;
    INST "iser_top2/iser_ddr_i0/dout_reg_0" LOC = SLICE_X54Y118;
    INST "iser_top1/iser_ddr_i1/dout_reg_1" BEL = BFF;
    INST "iser_top1/iser_ddr_i1/dout_reg_1" LOC = SLICE_X46Y110;
    INST "iser_top1/iser_ddr_i1/dout_reg_0" BEL = AFF;
    INST "iser_top1/iser_ddr_i1/dout_reg_0" LOC = SLICE_X46Y110;
    INST "iser_top2/iser_ddr_i1/dout_reg_1" BEL = BFF;
    INST "iser_top2/iser_ddr_i1/dout_reg_1" LOC = SLICE_X60Y112;
    INST "iser_top2/iser_ddr_i1/dout_reg_0" BEL = AFF;
    INST "iser_top2/iser_ddr_i1/dout_reg_0" LOC = SLICE_X60Y112;
    INST "iser_top1/iser_ddr_i2/dout_reg_1" BEL = BFF;
    INST "iser_top1/iser_ddr_i2/dout_reg_1" LOC = SLICE_X65Y94;
    INST "iser_top1/iser_ddr_i2/dout_reg_0" BEL = AFF;
    INST "iser_top1/iser_ddr_i2/dout_reg_0" LOC = SLICE_X65Y94;
    INST "iser_top2/iser_ddr_i2/dout_reg_1" BEL = BFF;
    INST "iser_top2/iser_ddr_i2/dout_reg_1" LOC = SLICE_X72Y90;
    INST "iser_top2/iser_ddr_i2/dout_reg_0" BEL = AFF;
    INST "iser_top2/iser_ddr_i2/dout_reg_0" LOC = SLICE_X72Y90;
    INST "iser_top1/iser_ddr_i3/dout_reg_1" BEL = CFF;
    INST "iser_top1/iser_ddr_i3/dout_reg_1" LOC = SLICE_X65Y109;
    INST "iser_top1/iser_ddr_i3/dout_reg_0" BEL = BFF;
    INST "iser_top1/iser_ddr_i3/dout_reg_0" LOC = SLICE_X65Y109;
    INST "iser_top2/iser_ddr_i3/dout_reg_1" BEL = CFF;
    INST "iser_top2/iser_ddr_i3/dout_reg_1" LOC = SLICE_X70Y87;
    INST "iser_top2/iser_ddr_i3/dout_reg_0" BEL = BFF;
    INST "iser_top2/iser_ddr_i3/dout_reg_0" LOC = SLICE_X70Y87;
    INST "iser_top1/iser_ddr_i4/dout_reg_1" BEL = DFF;
    INST "iser_top1/iser_ddr_i4/dout_reg_1" LOC = SLICE_X51Y112;
    INST "iser_top1/iser_ddr_i4/dout_reg_0" BEL = CFF;
    INST "iser_top1/iser_ddr_i4/dout_reg_0" LOC = SLICE_X51Y112;
    INST "iser_top2/iser_ddr_i4/dout_reg_1" BEL = CFF;
    INST "iser_top2/iser_ddr_i4/dout_reg_1" LOC = SLICE_X67Y110;
    INST "iser_top2/iser_ddr_i4/dout_reg_0" BEL = BFF;
    INST "iser_top2/iser_ddr_i4/dout_reg_0" LOC = SLICE_X67Y110;
    INST "iser_top1/iser_ddr_i5/dout_reg_1" BEL = BFF;
    INST "iser_top1/iser_ddr_i5/dout_reg_1" LOC = SLICE_X50Y108;
    INST "iser_top1/iser_ddr_i5/dout_reg_0" BEL = AFF;
    INST "iser_top1/iser_ddr_i5/dout_reg_0" LOC = SLICE_X50Y108;
    INST "iser_top2/iser_ddr_i5/dout_reg_1" BEL = CFF;
    INST "iser_top2/iser_ddr_i5/dout_reg_1" LOC = SLICE_X69Y108;
    INST "iser_top2/iser_ddr_i5/dout_reg_0" BEL = BFF;
    INST "iser_top2/iser_ddr_i5/dout_reg_0" LOC = SLICE_X69Y108;
    INST "iser_top1/iser_ddr_i6/dout_reg_1" BEL = DFF;
    INST "iser_top1/iser_ddr_i6/dout_reg_1" LOC = SLICE_X68Y90;
    INST "iser_top1/iser_ddr_i6/dout_reg_0" BEL = CFF;
    INST "iser_top1/iser_ddr_i6/dout_reg_0" LOC = SLICE_X68Y90;
    INST "iser_top2/iser_ddr_i6/dout_reg_1" BEL = BFF;
    INST "iser_top2/iser_ddr_i6/dout_reg_1" LOC = SLICE_X68Y87;
    INST "iser_top2/iser_ddr_i6/dout_reg_0" BEL = AFF;
    INST "iser_top2/iser_ddr_i6/dout_reg_0" LOC = SLICE_X68Y87;
    INST "iser_top1/iser_ddr_i7/dout_reg_1" BEL = BFF;
    INST "iser_top1/iser_ddr_i7/dout_reg_1" LOC = SLICE_X66Y80;
    INST "iser_top1/iser_ddr_i7/dout_reg_0" BEL = AFF;
    INST "iser_top1/iser_ddr_i7/dout_reg_0" LOC = SLICE_X66Y80;
    INST "iser_top2/iser_ddr_i7/dout_reg_1" BEL = CFF;
    INST "iser_top2/iser_ddr_i7/dout_reg_1" LOC = SLICE_X68Y79;
    INST "iser_top2/iser_ddr_i7/dout_reg_0" BEL = BFF;
    INST "iser_top2/iser_ddr_i7/dout_reg_0" LOC = SLICE_X68Y79;
    INST "data_clock_ctrl1/dco_buf_BUFG" LOC = BUFGCTRL_X0Y21;
    INST "data_clock_ctrl1/mmcm_top/mmcm_inst" LOC = MMCM_ADV_X0Y3;
    INST "data_clock_ctrl2/dco_buf_BUFG" LOC = BUFGCTRL_X0Y30;
    INST "data_clock_ctrl2/mmcm_top/mmcm_inst" LOC = MMCM_ADV_X0Y2;
    INST "iser_top1/BG1" LOC = BUFGCTRL_X0Y29;
    INST "iser_top2/BG1" LOC = BUFGCTRL_X0Y27;