Ad9253 signal acquisition test, F = 100.2mhz, FS =100MHz . Using Output Test Mode (1-/0-bit toggle), FPGA can correctly receive AAA8
Question: After passing the Output Test Mode interface Test, can it be considered that the transmission between LVDS data of ADC and FPGA is correct?

There will be some regular burrs in normal signal collection.

could you please give me some advise ?