AD9680 (using ad9680-1000ebz) clock-divider phase

Hi EZ,

I am evaluating AD9680. I connect the same signal to both Channels, I sample at 1GSPS and the data comes spot on the same.

However no matter what I select in 0x10C the data from ADC ChA vs ChB is never shifted by any clock delay. 

I've tried 1 GHz, with 1/2 divide.
I've tried 1 GHz and divide by 2, setting the ADC and link prams to 0.5 GSPS, and various divider phase settings also do nothing. ChaA data comes out always without any phase shift vs ChB

The DS says:

0x10C Clock divider phase (local)

"Independently controls Channel A and Channel B clock divider phase offset"

"The input clock divider inside the AD9680 provides phase delay in increments of ½ the input clock cycle. Register 0x10C can be programmed to enable this delay independently for each channel." 


How can I allegedly independently control ChA and ChB - if this is just one setting - there is no separate  setting for ChA and ChB