We want to use JESD204B interface based ADC AD9690-1000 with ARRIA 10 FPGA and in that we are using LTC6951 for clocking.
Now we want to interface 2.5V CML output of LTC6951 to LVDS interface of AD9690.
Our query is whether below interface given in datasheet is directly applicable between LTC6951 output and ADC CLK+/- input:-
Even if it is okay, are the values correct - 33E / 71E. I would have rather preferred the below one as it makes more sense as it gives differential Impedance of 100 ohm and common mode impedance of 75 ohm.
The reason why this doubt becomes more serious is that in DDC2226A schematic, the CML output simply interfaces LTC6951 output to ADC (some other ADC) using simple 100 ohm termination with AC coupling capacitor.
I am fully confused in this. I know it must be very basic and I may be missing things somewhere. But I am sure will get some help from this group as always.
By the way clocking frequency will be 819.2MHz