AD9690-1000 CLOCKING SOLUTION USING LTC6951

Hi,

We want to use JESD204B interface based ADC AD9690-1000 with ARRIA 10 FPGA and in that we are using LTC6951 for clocking.

Now we want to interface 2.5V CML output of LTC6951 to LVDS interface of AD9690.

Our query is whether below interface given in datasheet is directly applicable between LTC6951 output and ADC CLK+/- input:- 

Even if it is okay, are the values correct - 33E / 71E. I would have rather preferred the below one as it makes more sense as it gives differential Impedance of 100 ohm and common mode impedance of 75 ohm.

The reason why this doubt becomes more serious is that in DDC2226A schematic, the CML output simply interfaces LTC6951 output to ADC (some other ADC) using simple 100 ohm termination with AC coupling capacitor.

I am fully confused in this. I know it must be very basic and I may be missing things somewhere. But I am sure will get some help from this group as always.

By the way clocking frequency will be 819.2MHz

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  • +1
    •  Analog Employees 
    on Sep 16, 2021 7:29 PM

    Sorry for the conflicting recommendations.  Please use this schematic between the LTC6951 and AD9690.

    The CML schematic in the AD9690 was for a different CML clock IC that is no longer offered by ADI.

  • Hi Chris,

    Thanks a lot. We hope that it would be corrected in the Datasheet.

    If you permit, I would like to know whether the same interface can be used to buffer JESD SYSREF Buffering between LTC6951 and LTC6957. Right now I have used the below design, if the below one is okay.

    Thanks a lot Chris

  • +1
    •  Analog Employees 
    on Sep 20, 2021 1:22 PM in reply to MohitH

    For a continuous SYSREF AC coupling between the LTC6951 and LTC6957 as shown above will work great.  If you are going to stop the LTC6951 STOP output (MUTE bits in LTC6951 register map), then DC coupling is preferred.  In this case, it is possible to change C1304 and C1303 to 0 ohm resistors, as both the LTC6951 outputs and the LTC6957 input have similar common mode voltages.

  • Thanks Chris for your reply.

    Just wanted to know on one basic thing here. At some places we find AC coupling CAPs behind termination resistors and at other places, we find them after termination resisters. 

    I am still not very clear why at all this may make a difference.

  • +1
    •  Analog Employees 
    on Sep 23, 2021 3:36 PM in reply to MohitH

    From a theoretical signal integrity point of view, the 100 ohm termination should be as close as possible to the receiving device.  If possible placing the 100 ohm resistor after the AC coupling caps allows for the 100 ohm resistor to be place closer to the receiving device.  That's the theory, but practically speak for many devices either method works, so you will see some variation in schematics for this reason alone.

    However, some times there are other considerations. 

    For instance, LVDS needs a DC with the 100 ohm resistor before the ac coupling caps to work correctly.

    Or the LTC6951/LTC6952 CML outputs will need the 100 ohm before the AC coupling caps if the first starting clock edge level is important.  However, if the first clock edge is not important, placing the 100 ohm after AC coupling caps is better for signal integrity.

    LVPECL requires a DC pull-down path to GND somewhere in its termination network. LVPECL  has several different termination schemes, so it will depend on which termination scheme chosen as to what is best.

    It's also possible the receiving devices will have strange internal input network that may affect the placement of the 100 ohm resistor.

Reply
  • +1
    •  Analog Employees 
    on Sep 23, 2021 3:36 PM in reply to MohitH

    From a theoretical signal integrity point of view, the 100 ohm termination should be as close as possible to the receiving device.  If possible placing the 100 ohm resistor after the AC coupling caps allows for the 100 ohm resistor to be place closer to the receiving device.  That's the theory, but practically speak for many devices either method works, so you will see some variation in schematics for this reason alone.

    However, some times there are other considerations. 

    For instance, LVDS needs a DC with the 100 ohm resistor before the ac coupling caps to work correctly.

    Or the LTC6951/LTC6952 CML outputs will need the 100 ohm before the AC coupling caps if the first starting clock edge level is important.  However, if the first clock edge is not important, placing the 100 ohm after AC coupling caps is better for signal integrity.

    LVPECL requires a DC pull-down path to GND somewhere in its termination network. LVPECL  has several different termination schemes, so it will depend on which termination scheme chosen as to what is best.

    It's also possible the receiving devices will have strange internal input network that may affect the placement of the 100 ohm resistor.

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