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AD9874 - Random DC offset in IQ data

Dear colleagues,

After the AD9874 startup I have constant DC offset in IQ data. This offset is constant until the next AD9874 startup. Each startup results in in different offset value. In most cases the offset is too big and results in unacceptable system behavior. But once per 20-40 attempts of AD9874 startup, the offset in IQ data is negligible and system works as I want.

LNA input signal (70MHz) is AM modulated carrier (1 kHz, 30 %), at a level equal to the sensitivity level of my system. This carrier has 4 kHz offset to the center of the receiver channel (to be distinguished from the DC offset). IQ sampling frequency is equal to 75 kHz.

First I present signals when DC offset is too big.

Amplitude spectrum of the IQ signal (FFT from 1024 IQ samples) is presented below. DC offset is at level comparable to the side lobes of AM modulation.

1024 samples of the raw I signal and low pass filtered I signal are presented below. It is visible, that a mean value of I signal is about 300 LSB.

1024 samples of IQ signals (I blue, Q red) are presented below.

Spectrum of AM demodulation ( sqrt(I^2 + Q^2) plus filters ) of the presented signal is shown below:

The 4 kHz component is too big and too audible.

 

Now I present the signals when the DC offset is negligible.

FFT form IQ signals – there is almost no 0 IF spur. Only AM modulated carrier is present in the spectrum.

Raw I signal and low pass filtered I signal – mean value close to 0 LSB:

 

Raw IQ signals:

 

Spectrum of the AM demodulation – it is visible, that 4 kHz spur is at least 20 dB lower in comparison to the situation with DC offset.

 

The questions are:

  • how to get no offset in a predictable way?
  • What is the origin of that offset?

What I have done until now during the problem investigation.

  • All results are measured on our hardware (not AD9874 Evaluation Board). It is repeatable on three instances of PCB.
  • I’ve ensured, that signal on LNA input is clear and has no 0 IF components.
  • AD9874 is programmed by embedded system in the same predictable way. After each configuration data sending over SPI I read the registers of AD9874 – the values in registers are compliant with sent ones.
  • I send the reset command at the beginning of the initialization. 3 ms delay is added between CLK synthesizer configuration and start of ADC tuning procedure. I’m waiting 6 ms until AD9874 tune is finished. Tuning is finished with value 0x00 in 0x1C register. RC and LC tuning registers are within 25%...75% of its allowed value. After each tuning Cap R = 99, CAPL1(coarse) = 3, CAPL2(fine) = 11+/-1;
  • When I connect a signal (using transformer) directly to the delta-sigma converter input (at frequency 2.25MHz, pins IF2P IF2N), there is no problem with DC offset and the results are excellent. We didn’t try use hung mixer mode.
  • I didn’t check how the offset changes with temperature.
  • SYNCB line of AD9874 is in high state all the time
  • I tried different sequencies of configuration command:
    1. Based on the AD9874 specification (no factory registers are used)
    2. Based on the AD9864 specification (factory registers are used)
    3. Based on the sequences provided with the AD9874 Evaluation Board (factory registers are used)

      In each case there is no difference related to the DC offset.
      By the way – where I can find recommended sequence of the ADC tuning?

 Do you have any hints how eliminate the offset?

Best regards

Igor

Parents
  • Hello,

    Since the LNA is single-ended, it is susceptible to digital noise contamination that may come from the data path clocks as well as the SSI block.  If one refers to Figure 23b.................one can see the level of in-band spurious that still exists excluding the LO frequencies that are known to produce large-in band spurs.

    Things to try are as follows:

    1) Since decimation factor is 240...................one can either use K=0 or K=1 when configuring the decimation factor since both 240 is divisible by 60 or 48.   See if choosing the other K value will corresponding M value to maintain 240 overall decimation factor makes any difference since this changes the internal digital clock rae.

    2) To determine if it is due to the SSI block...............one can try a different  SSIORD setting that meets equation 1 (page 17) along with lower output drive strength (page 18) to see if that improves spur level.   

    3) One can also see if operation at a lower supply level (since AD9874 can operate over a 2.7 to 3.6 V span) can provide some improvement since lower supply reduces the rise/fall times of digital circuitry.


    With regard to best SPI initialization procedure................please refer to the AD9864 datasheet which was updated in 2016 and includes a example SPI initialization procedure on page 47. 

    Regards.

Reply
  • Hello,

    Since the LNA is single-ended, it is susceptible to digital noise contamination that may come from the data path clocks as well as the SSI block.  If one refers to Figure 23b.................one can see the level of in-band spurious that still exists excluding the LO frequencies that are known to produce large-in band spurs.

    Things to try are as follows:

    1) Since decimation factor is 240...................one can either use K=0 or K=1 when configuring the decimation factor since both 240 is divisible by 60 or 48.   See if choosing the other K value will corresponding M value to maintain 240 overall decimation factor makes any difference since this changes the internal digital clock rae.

    2) To determine if it is due to the SSI block...............one can try a different  SSIORD setting that meets equation 1 (page 17) along with lower output drive strength (page 18) to see if that improves spur level.   

    3) One can also see if operation at a lower supply level (since AD9874 can operate over a 2.7 to 3.6 V span) can provide some improvement since lower supply reduces the rise/fall times of digital circuitry.


    With regard to best SPI initialization procedure................please refer to the AD9864 datasheet which was updated in 2016 and includes a example SPI initialization procedure on page 47. 

    Regards.

Children
  • Hi,

    I probably identified the problem's origin. I use AD9874 Eval Board. Reference clock on the eval board = 26 MHz. Synth clock set to 18 MHz – it results in 2.25 MHz of IF band-pass sigma-delta frequency. Clock synthesizer’s comparison frequency equal to 26MHz*90/130 = 200 kHz. 200 kHz harmonics nearest to 2.25 MHz are [2.2, 2.4] MHz. Therefore, no spurs from clock synthesizers are in the ADC band.

    Now I manipulate LO synthesizer.

    Example 1.

    LO comparison freq = 26MHz / 81 = 320987.65 Hz.

    Its 7-th harmonic is equal to 320987.65 Hz * 7 = 2.2469136 MHz.

    2.25 MHz - 2.2469136 MHz = -3086 Hz. See spectrum below.

     

    Example 2.

    LO comparison freq = 26MHz / 104 = 250000 Hz.

    Its 9-th harmonic is equal to 250000 Hz * 9 = 2.25 MHz.

    2.25 MHz - 2.25 MHz = 0 Hz. See spectrum below.

     

    Example 3.

    LO comparison freq = 26MHz / 127 = 204724.41 Hz.

    Its 11-th harmonic is equal to 204724.41 Hz * 11 = 2.2519685 MHz.

    2.2519685 MHz - 2.25 MHz = 1968 Hz. See spectrum below.

     

    Example 4.

    LO comparison freq = 26MHz / 150 = 173333.33 Hz.

    Its 13-th harmonic is equal to 173333.33 Hz * 13 = 2.2533333 MHz.

    2.2533333 MHz - 2.25 MHz = 3333 Hz. See spectrum below.

     

    Best regards

    Igor