Products In This Thread

AD9213 Recommended for New Designs
The AD9213 is a single, 12-bit, 6 GSPS/10.25 GSPS, radio frequency (RF) analog-to-digital converter (ADC) with a 6.5 GHz input bandwidth. The AD9213 supports...
Datasheet
AD9213 on Analog.com

  • State Suggested Answer
  • +1 person also asked this people also asked this
  • Replies 7 replies
  • Answers 1 answer
  • Subscribers 44 subscribers
  • Views 1315 views
  • Users 0 members are here
Options
Related 

        

            Post
             Go back to editing
        

    

    


    

    









		












	
	
			
	
			
		
	
	
		

		
AD9213: Test Pattern Incorrect



		

			

									
					    mgarrett
					
							

			
				
									
											
			
			
				
    
			
			
			    	
			                    
                
				                on Sep 12, 2021 
				
			
			
		
    

				
		
    
		    		    
		    
		    	
			
    Hi,
    

    I’m attempting to bring up the AD9213 (https://www.analog.com/media/en/technical-documentation/data-sheets/AD9213.pdf) ADC on an FMC mezzanine card connected to a Xilinx Ultrascale+ VU13P FGPA (using the LogicCore JESD204 v7.2 IP).  I’m initially trying to bring up the JESD204 interface into an alternating checkerboard test pattern from the ADC.  The relevant parameters and corresponding register settings are shown below where applicable.
    

      

    1. L = 16 (# of lanes)

        

      1. AD9213 - JTX_SCR_L_CFG (0x0520) = 0x000F
        2. 

      2. JESD204 Core – Lanes in Use (0x0028) = 0xFF
        3. 

      

      2. 

    2. F = 2 (octets per frame)

        

      1. AD9213 - JTX_F_CFG (0x0521) = 0x0001
        2. 

      2. JESD204 Core – Octets per Frame (0x0020) = 0x0001
        3. 

      

      3. 

    3. K = 32 (frames per multiframe)

        

      1. AD9213 - JTX_K_CFG (0x0522) = 0x001F
        2. 

      2. JESD204 Core – Frames per Multiframe (0x0024) = 0x001F
        3. 

      

      4. 

    4. N = 12 (converter resolution)

        

      1. AD9213 - JTX_CS_N_CFG (0x0524) = 0x000B
        2. 

      

      5. 

    5. N’ = 16 (bits per sample)

        

      1. AD9213 - JTX_SCV_NP_CFG = (0x0525) = 0x000F
        2. 

      

      6. 

    6. M = 1 (# of converters)

        

      1. AD9213 - JTX_M_CFG (0x0523) = 0x0000
        2. 

      

      7. 

    7. CS = 0 (# of control bits)

        

      1. AD9213 - JTX_CS_N_CFG (0x0524) = 0x000B
        2. 

      

      8. 

    8. Subclass: 0

        

      1. AD9213 - JTX_SCV_NP_CFG (0x0525) = 0x000F
        2. 

      

      9. 

    9. Scrambling: Disabled

        

      1. AD9213 - JTX_SCR_L_CFG (0x0520) = 0x000F
        2. 

      2. JESD204 Core – Device Subclass (0x002C) = 0x0000
        3. 

      

      10. 

    10. Test Mode: Alternating checkerboard

        

      1. AD9213 - JTX_LINK_CTRL1 (0x0503) = 0x0014
        2. 

      2. AD9213 - JTX_LINK_CTRL2 (0x0504) = 0x00C0
        3. 

      3. AD9213 - JTX_LINK_CTRL3 (0x0505) = 0x0001
        4. 

      4. AD9213 - JTX_LINK_CTRL4 (0x0506) = 0x0000
        5. 

      5. AD9213 - JTX_LINK_CTRL5 (0x0507) = 0x0000
        6. 

      6. JESD204 Core – Test Modes (0x0018) = 0x0000
        7. 

      

      11. 

    11. Physical Parameters:

        

      1. AD9213 Sampling clock = 10GHz
        2. 

      2. JESD204 ref clock (1 per JESD204 core) = 312.5MHz
        3. 

      3. JESD204 core clock = 312.5MHz
        4. 

      4. Lane rate = 12.5 Gbps
        5. 

      5. Clocking and JESD204 configuration matches guidelines here: https://www.xilinx.com/support/answers/71575.html
        6. 

      

      12. 

    

    The issue is that the expected checkerboard data isn’t observed when probing the gt#_rxdata lanes. However, between runs (reprogramming, no power-cycle) the test pattern appears correct intermittently across different GTY4E transceiver lanes as shown below.  Changing the test pattern to toggling 0/1 shows the same pattern so I know that at least some correct data is showing up.
    

     
    

    For another data point, if I program the AD9213 to operate in normal mode (not test mode), I do see that the JESD204 core is reporting unexpected K-characters via the JESD204 Link Error Status registers.
    

     
    

    ************************JESD 0***********************
    

            ILA Support(0x08) = 0x1
    

            Scrambling(0x0C) = 0x0
    

            SYSREF Handling(0x10) = 0x1
    

            Test Modes(0x18) = 0x0
    

            Link Error Status(0x1C) = 0x924924
    

            Octets per Frame(0x20) = 0x1
    

            Frames per Multiframe(0x24) = 0x1F
    

            Lanes in Use(0x28) = 0xFF
    

            Subclass Mode(0x2C) = 0x0
    

            RX Buffer Delay(0x30) = 0x0
    

            Error Reporting(0x34) = 0x1
    

            Sync Status(0x38) = 0x1
    

            Debug Status(0x3C) = 0xEEEEEEEE
    

            Link Error Counts:0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0
    

    *********************************************************
    

    ************************JESD 1***********************
    

            ILA Support(0x08) = 0x1
    

            Scrambling(0x0C) = 0x0
    

            SYSREF Handling(0x10) = 0x1
    

            Test Modes(0x18) = 0x0
    

            Link Error Status(0x1C) = 0x924924
    

            Octets per Frame(0x20) = 0x1
    

            Frames per Multiframe(0x24) = 0x1F
    

            Lanes in Use(0x28) = 0xFF
    

            Subclass Mode(0x2C) = 0x0
    

            RX Buffer Delay(0x30) = 0x0
    

            Error Reporting(0x34) = 0x1
    

            Sync Status(0x38) = 0x1
    

            Debug Status(0x3C) = 0xEEEEEEEE
    

            Link Error Counts:0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0
    

    

    The two issues are seemingly related (scrambled checkerboard pattern and unexpected K-characters) but I haven’t yet root-caused.  Here is what I’ve tried so far:
    

      

    1. Check eye-diagram with In-System IBERT.

        

      1. One observation here is that the eye appears closed intermittently across different lanes. Reconfiguring (no power-cycle) produces different results.  Sometimes, all eye diagrams are open.
        2. 

      2.  
        3. 

      

      2. 

    2. Adjusting insertion loss settings on the JESD204 PHY seems to have no impact on test pattern or IBERT eye scans.
      3. 

    3. Reducing the ADC sampling clock to 8GHz (JESD clocks at 250MHz, lane rate = 10Gbps) has no impact.
      4. 

    

    See attached for register dumps of the AD9213 and JESD204 core in both normal and test modes.



    
    
    
        Fullscreen
        ad9213_regs_normal_mode.txt
        Download
    
    
    
    SPI_CONFIG_A                        (0x0000) = 0x0024
DEVICE_CONFIG                       (0x0002) = 0x00F0
CHIP_TYPE                           (0x0003) = 0x0003
CHIP_ID_LSB                         (0x0004) = 0x00E5
CHIP_ID_MSB                         (0x0005) = 0x0000
CHIP_SCRATCH                        (0x000A) = 0x00BC
VENDOR_ID_LSB                       (0x000C) = 0x0056
VENDOR_ID_MSB                       (0x000D) = 0x0004
CHIP_GEN_CTRL                       (0x0026) = 0x0000
FD_CTRL                             (0x0100) = 0x0000
FD_UP_THRESH_LSB                    (0x0101) = 0x0000
FD_UP_THRESH_MSB                    (0x0102) = 0x0000
FD_LOW_THRESH_LSB                   (0x0103) = 0x0000
FD_LOW_THRESH_MSB                   (0x0104) = 0x0000
FD_DWELL_THRESH_LSB                 (0x0105) = 0x0000
FD_DWELL_THRESH_MSB                 (0x0106) = 0x0000
SMON_STATUS_0                       (0x0120) = 0x0000
SMON_STATUS_1                       (0x0121) = 0x0000
SMON_STATUS_2                       (0x0122) = 0x0000
SMON_STATUS_FCNT                    (0x0123) = 0x0000
SMON_PERIOD_0                       (0x0124) = 0x0000
SMON_PERIOD_1                       (0x0125) = 0x0000
SMON_PERIOD_2                       (0x0126) = 0x0000
SMON_STATUS_CTRL                    (0x0127) = 0x0000
SMON_SFRAMER                        (0x0128) = 0x0000
SMON_SYNC_CTRL                      (0x0129) = 0x0000
SMON_CLK_EN                         (0x0131) = 0x0000
CLK_CHG_REQ                         (0x0332) = 0x0000
PLL_CTRL                            (0x0500) = 0x0000
PLL_STATUS                          (0x0501) = 0x0080
JTX_LINK_CTRL1                      (0x0503) = 0x0014
JTX_LINK_CTRL2                      (0x0504) = 0x0000
JTX_LINK_CTRL3                      (0x0505) = 0x0000
JTX_LINK_CTRL4                      (0x0506) = 0x0000
JTX_LINK_CTRL5                      (0x0507) = 0x0000
JTX_SYNC_CTRL                       (0x0508) = 0x0020
JTX_CS_BITS_CTRL                    (0x0509) = 0x0002
JTX_LMFC_OFFSET                     (0x050A) = 0x0000
JTX_DID_CFG                         (0x050E) = 0x0000
JTX_BID_CFG                         (0x050F) = 0x0000
JTX_LID0_CFG                        (0x0510) = 0x0000
JTX_LID1_CFG                        (0x0511) = 0x0001
JTX_LID2_CFG                        (0x0512) = 0x0002
JTX_LID3_CFG                        (0x0513) = 0x0003
JTX_LID4_CFG                        (0x0514) = 0x0004
JTX_LID5_CFG                        (0x0515) = 0x0005
JTX_LID6_CFG                        (0x0516) = 0x0006
JTX_LID7_CFG                        (0x0517) = 0x0007
JTX_LID8_CFG                        (0x0518) = 0x0008
JTX_LID9_CFG                        (0x0519) = 0x0009
JTX_LID10_CFG                       (0x051A) = 0x000A
JTX_LID11_CFG                       (0x051B) = 0x000B
JTX_LID12_CFG                       (0x051C) = 0x000C
JTX_LID13_CFG                       (0x051D) = 0x000D
JTX_LID14_CFG                       (0x051E) = 0x000E
JTX_LID15_CFG                       (0x051F) = 0x000F
JTX_SCR_L_CFG                       (0x0520) = 0x000F
JTX_F_CFG                           (0x0521) = 0x0001
JTX_K_CFG                           (0x0522) = 0x001F
JTX_M_CFG                           (0x0523) = 0x0000
JTX_CS_N_CFG                        (0x0524) = 0x000B
JTX_SCV_NP_CFG                      (0x0525) = 0x000F
JTX_JV_S_CFG                        (0x0526) = 0x002F
JTX_HD_CF_CFG                       (0x0527) = 0x0000
JTX_CHKSUM0_CFG                     (0x052B) = 0x0078
JTX_CHKSUM1_CFG                     (0x052C) = 0x0079
JTX_CHKSUM2_CFG                     (0x052D) = 0x007A
JTX_CHKSUM3_CFG                     (0x052E) = 0x007B
JTX_CHKSUM4_CFG                     (0x052F) = 0x007C
JTX_CHKSUM5_CFG                     (0x0530) = 0x007D
JTX_CHKSUM6_CFG                     (0x0531) = 0x007E
JTX_CHKSUM7_CFG                     (0x0532) = 0x007F
JTX_CHKSUM8_CFG                     (0x0533) = 0x0080
JTX_CHKSUM9_CFG                     (0x0534) = 0x0081
JTX_CHKSUM10_CFG                    (0x0535) = 0x0082
JTX_CHKSUM11_CFG                    (0x0536) = 0x0083
JTX_CHKSUM12_CFG                    (0x0537) = 0x0084
JTX_CHKSUM13_CFG                    (0x0538) = 0x0085
JTX_CHKSUM14_CFG                    (0x0539) = 0x0086
JTX_CHKSUM15_CFG                    (0x053A) = 0x0087
JTX_LANE_PDWN                       (0x053B) = 0x0000
JTX_LANE_PDWN2                      (0x053C) = 0x0000
JTX_LANE_ASSIGN1                    (0x053D) = 0x0010
JTX_LANE_ASSIGN2                    (0x053E) = 0x0032
JTX_LANE_ASSIGN3                    (0x053F) = 0x0054
JTX_LANE_ASSIGN4                    (0x0540) = 0x0076
JTX_LANE_ASSIGN5                    (0x0541) = 0x0098
JTX_LANE_ASSIGN6                    (0x0542) = 0x00BA
JTX_LANE_ASSIGN7                    (0x0543) = 0x00DC
JTX_LANE_ASSIGN8                    (0x0544) = 0x00FE
JTX_QBF_STATUS_REG                  (0x0547) = 0x0000
JTX_TEST_GEN_INV                    (0x0557) = 0x0000
CHIP_USR_PAT_1_7_0                  (0x0558) = 0x0000
CHIP_USR_PAT_1_15_8                 (0x0559) = 0x0000
CHIP_USR_PAT_2_7_0                  (0x055A) = 0x0000
CHIP_USR_PAT_2_15_8                 (0x055B) = 0x0000
CHIP_USR_PAT_3_7_0                  (0x055C) = 0x0000
CHIP_USR_PAT_3_15_8                 (0x055D) = 0x0000
CHIP_USR_PAT_4_7_0                  (0x055E) = 0x0000
CHIP_USR_PAT_4_15_8                 (0x055F) = 0x0000
SER_PARITY_RESET_EN1                (0x0560) = 0x0000
SER_PARITY_RESET_EN2                (0x0561) = 0x0000
SER_PARITY_ERR1                     (0x0564) = 0x0000
SER_PARITY_ERR2                     (0x0565) = 0x0000
PLL_ENABLE_CTRL                     (0x0570) = 0x0001
JESD_S_CFG                          (0x0591) = 0x0000
JESD_HD_CF_CFG                      (0x0592) = 0x0000
PWR_DN                              (0x05B0) = 0x0000
PWR_DN2                             (0x05B1) = 0x0000
DDC_SYNC_CTRL                       (0x0600) = 0x0002
DDC_SYNC_STATUS                     (0x0601) = 0x0000
DDC_TRIG_CTRL                       (0x0602) = 0x0000
CHIP_DP_MODE                        (0x0606) = 0x0020
CHIP_DEC_RATIO                      (0x0607) = 0x0000
CHIP_RES_0                          (0x0608) = 0x0000
CHIP_RES_1                          (0x0609) = 0x0000
CTRL_0_1_SEL                        (0x0620) = 0x0000
CTRL_2_SEL                          (0x0621) = 0x0000
OUT_FORMAT_SEL                      (0x0622) = 0x0000
OVR_STATUS                          (0x0623) = 0x0000
OVR_CLR                             (0x0624) = 0x0000
OUT_CHAN_SEL                        (0x0625) = 0x0000
OUT_RES                             (0x0626) = 0x0000
DDC_CTRL                            (0x0630) = 0x0000
DDC_DEC_CTRL                        (0x0631) = 0x0000
DDC_NCO_CTRL                        (0x0632) = 0x0000
DDC_PROFILE_CTRL                    (0x0633) = 0x0000
DDC_PHASE_INC0                      (0x0634) = 0x0000
DDC_PHASE_INC1                      (0x0635) = 0x0000
DDC_PHASE_INC2                      (0x0636) = 0x0000
DDC_PHASE_INC3                      (0x0637) = 0x0000
DDC_PHASE_INC4                      (0x0638) = 0x0000
DDC_PHASE_INC5                      (0x0639) = 0x0000
DDC_PHASE_OFFSET0                   (0x063A) = 0x0000
DDC_PHASE_OFFSET1                   (0x063B) = 0x0000
DDC_PHASE_OFFSET2                   (0x063C) = 0x0000
DDC_PHASE_OFFSET3                   (0x063D) = 0x0000
DDC_PHASE_OFFSET4                   (0x063E) = 0x0000
DDC_PHASE_OFFSET5                   (0x063F) = 0x0000
DDC_PHASE_INC_FRAC_A0               (0x0640) = 0x0000
DDC_PHASE_INC_FRAC_A1               (0x0641) = 0x0000
DDC_PHASE_INC_FRAC_A2               (0x0642) = 0x0000
DDC_PHASE_INC_FRAC_A3               (0x0643) = 0x0000
DDC_PHASE_INC_FRAC_A4               (0x0644) = 0x0000
DDC_PHASE_INC_FRAC_A5               (0x0645) = 0x0000
DDC_PHASE_INC_FRAC_B0               (0x0646) = 0x0000
DDC_PHASE_INC_FRAC_B1               (0x0647) = 0x0000
DDC_PHASE_INC_FRAC_B2               (0x0648) = 0x0000
DDC_PHASE_INC_FRAC_B3               (0x0649) = 0x0000
DDC_PHASE_INC_FRAC_B4               (0x064A) = 0x0000
DDC_PHASE_INC_FRAC_B5               (0x064B) = 0x0000
DDC_TRANSFER_CTRL                   (0x064C) = 0x0000
DDC_TRANSFER_STATUS                 (0x064D) = 0x0000
MOD_NCO_PHASE_ERROR_LOAD_REG0       (0x0650) = 0x0000
MOD_NCO_PHASE_ERROR_LOAD_REG1       (0x0651) = 0x0000
MOD_NCO_PHASE_ERROR_LOAD_REG2       (0x0652) = 0x0000
MOD_NCO_PHASE_ERROR_LOAD_REG3       (0x0653) = 0x0000
MOD_NCO_PHASE_ERROR_LOAD_REG4       (0x0654) = 0x0000
MOD_NCO_PHASE_ERROR_LOAD_REG5       (0x0655) = 0x0000
MOD_NCO_PHASE_ERROR_LOAD_REG6       (0x0656) = 0x0000
NCO_PHASE_ERROR_LOAD_STATUS         (0x0657) = 0x0000
DDC_PSW_0                           (0x065F) = 0x0000
DDC_PSW_1                           (0x0660) = 0x0000
DDC_PSW_2                           (0x0661) = 0x0000
DDC_PSW_3                           (0x0662) = 0x0000
DDC_PSW_4                           (0x0663) = 0x0000
DDC_PSW_5                           (0x0664) = 0x0000
DDC_ACTIVE_PHASE_INC0               (0x0665) = 0x0000
DDC_ACTIVE_PHASE_INC1               (0x0666) = 0x0000
DDC_ACTIVE_PHASE_INC2               (0x0667) = 0x0000
DDC_ACTIVE_PHASE_INC3               (0x0668) = 0x0000
DDC_ACTIVE_PHASE_INC4               (0x0669) = 0x0000
DDC_ACTIVE_PHASE_INC5               (0x066A) = 0x0000
DDC_ACTIVE_PHASE_OFFSET0            (0x066B) = 0x0000
DDC_ACTIVE_PHASE_OFFSET1            (0x066C) = 0x0000
DDC_ACTIVE_PHASE_OFFSET2            (0x066D) = 0x0000
DDC_ACTIVE_PHASE_OFFSET3            (0x066E) = 0x0000
DDC_ACTIVE_PHASE_OFFSET4            (0x066F) = 0x0000
DDC_ACTIVE_PHASE_OFFSET5            (0x0670) = 0x0000
TIMESTAMP_READ_CTRL                 (0x0671) = 0x0000
TIMESTAMP_COUNTER_REG0              (0x0672) = 0x0000
TIMESTAMP_COUNTER_REG1              (0x0673) = 0x0000
TIMESTAMP_COUNTER_REG2              (0x0674) = 0x0000
TIMESTAMP_COUNTER_REG3              (0x0675) = 0x0000
TIMESTAMP_COUNTER_REG4              (0x0676) = 0x0000
TIMESTAMP_COUNTER_REG5              (0x0677) = 0x0000
TIMESTAMP_COUNTER_REG6              (0x0678) = 0x0000
TIMESTAMP_COUNTER_REG7              (0x0679) = 0x0000
JTX_CLK                             (0x0681) = 0x0010
SYSREF_DELAY                        (0x0690) = 0x0000
TRIG_DELAY                          (0x0691) = 0x0000
TIMESTAMP_DELAY                     (0x0692) = 0x0000
SYSREF_RESYNC                       (0x0693) = 0x0000
SYSREF_CTRL                         (0x1508) = 0x0000
SYSREF_STATUS                       (0x1509) = 0x0064
LVDS_SEL                            (0x150A) = 0x0000
SPI_EN_DCS                          (0x150C) = 0x0000
SPI_EN_FDLY                         (0x150D) = 0x0000
SPI_TRM_FINE_DLY                    (0x150E) = 0x0000
SPI_TRM_SUPER_FINE_DLY              (0x150F) = 0x0000
SPI_SFDC_BYPASS                     (0x1510) = 0x0000
BKEND_TOP_GAIN_ADJ                  (0x1511) = 0x0000
SUPPLY_MON1                         (0x1512) = 0x003F
SUPPLY_MON2                         (0x1513) = 0x001F
SUPPLY_MON3                         (0x1514) = 0x0003
PDOWN_CTRL                          (0x1515) = 0x00FC
SPI_EN_FDLY_SYS                     (0x1516) = 0x0000
SPI_TRM_FINE_DLY_SYS                (0x1517) = 0x0000
SPI_TRM_SUPER_FINE_DLY_SYS          (0x1518) = 0x0000
SPI_SFDC_BYPASS_SYS                 (0x1519) = 0x0000
EN_VCM_MODE                         (0x151A) = 0x0001
SPI_NVG1                            (0x151B) = 0x0005
CLOCK_DETECT_CTRL                   (0x151D) = 0x0003
MCS_CTRL                            (0x151E) = 0x0000
MCS_SYSREF_IGNORE_COUNT             (0x1521) = 0x0000
USER_CTRL_TRANSFER                  (0x1600) = 0x0000
CAL_CONTROL                         (0x1601) = 0x0000
MAX_TEMPERATURE_LSB                 (0x1609) = 0x00DF
MAX_TEMPERATURE_MSB                 (0x160A) = 0x002A
MIN_TEMPERATURE_LSB                 (0x160D) = 0x00C6
MIN_TEMPERATURE_MSB                 (0x160E) = 0x0027
MCS_MODE                            (0x1621) = 0x0000
MCS_CTRL                            (0x1622) = 0x0000
MCS_CALC_TIME_DIFF1                 (0x1623) = 0x0000
MCS_CALC_TIME_DIFF2                 (0x1624) = 0x0000
MCS_CALC_TIME_DIFF3                 (0x1625) = 0x0000
MCS_CALC_TIME_DIFF4                 (0x1626) = 0x0000
MCS_KNOWN_SYSREF_PERIOD1            (0x1627) = 0x0000
MCS_KNOWN_SYSREF_PERIOD2            (0x1628) = 0x0000
MCS_KNOWN_SYSREF_PERIOD3            (0x1629) = 0x0000
MCS_SAMPLE_CLK_PERIOD1              (0x162D) = 0x0000
MCS_SAMPLE_CLK_PERIOD2              (0x162E) = 0x0000
MCS_SAMPLE_CLK_PERIOD3              (0x162F) = 0x0000
MCS_SAMPLE_CLK_PERIOD4              (0x1630) = 0x0000
MCS_PHASE_SLIP_MODE                 (0x1636) = 0x0000
    

    





    
    
    
        Fullscreen
        ad9213_regs_test_mode.txt
        Download
    
    
    
    SPI_CONFIG_A                        (0x0000) = 0x0024
DEVICE_CONFIG                       (0x0002) = 0x00F0
CHIP_TYPE                           (0x0003) = 0x0003
CHIP_ID_LSB                         (0x0004) = 0x00E5
CHIP_ID_MSB                         (0x0005) = 0x0000
CHIP_SCRATCH                        (0x000A) = 0x00BC
VENDOR_ID_LSB                       (0x000C) = 0x0056
VENDOR_ID_MSB                       (0x000D) = 0x0004
CHIP_GEN_CTRL                       (0x0026) = 0x0000
FD_CTRL                             (0x0100) = 0x0000
FD_UP_THRESH_LSB                    (0x0101) = 0x0000
FD_UP_THRESH_MSB                    (0x0102) = 0x0000
FD_LOW_THRESH_LSB                   (0x0103) = 0x0000
FD_LOW_THRESH_MSB                   (0x0104) = 0x0000
FD_DWELL_THRESH_LSB                 (0x0105) = 0x0000
FD_DWELL_THRESH_MSB                 (0x0106) = 0x0000
SMON_STATUS_0                       (0x0120) = 0x0000
SMON_STATUS_1                       (0x0121) = 0x0000
SMON_STATUS_2                       (0x0122) = 0x0000
SMON_STATUS_FCNT                    (0x0123) = 0x0000
SMON_PERIOD_0                       (0x0124) = 0x0000
SMON_PERIOD_1                       (0x0125) = 0x0000
SMON_PERIOD_2                       (0x0126) = 0x0000
SMON_STATUS_CTRL                    (0x0127) = 0x0000
SMON_SFRAMER                        (0x0128) = 0x0000
SMON_SYNC_CTRL                      (0x0129) = 0x0000
SMON_CLK_EN                         (0x0131) = 0x0000
CLK_CHG_REQ                         (0x0332) = 0x0000
PLL_CTRL                            (0x0500) = 0x0000
PLL_STATUS                          (0x0501) = 0x0080
JTX_LINK_CTRL1                      (0x0503) = 0x0014
JTX_LINK_CTRL2                      (0x0504) = 0x00C0
JTX_LINK_CTRL3                      (0x0505) = 0x0001
JTX_LINK_CTRL4                      (0x0506) = 0x0000
JTX_LINK_CTRL5                      (0x0507) = 0x0000
JTX_SYNC_CTRL                       (0x0508) = 0x0020
JTX_CS_BITS_CTRL                    (0x0509) = 0x0002
JTX_LMFC_OFFSET                     (0x050A) = 0x0000
JTX_DID_CFG                         (0x050E) = 0x0000
JTX_BID_CFG                         (0x050F) = 0x0000
JTX_LID0_CFG                        (0x0510) = 0x0000
JTX_LID1_CFG                        (0x0511) = 0x0001
JTX_LID2_CFG                        (0x0512) = 0x0002
JTX_LID3_CFG                        (0x0513) = 0x0003
JTX_LID4_CFG                        (0x0514) = 0x0004
JTX_LID5_CFG                        (0x0515) = 0x0005
JTX_LID6_CFG                        (0x0516) = 0x0006
JTX_LID7_CFG                        (0x0517) = 0x0007
JTX_LID8_CFG                        (0x0518) = 0x0008
JTX_LID9_CFG                        (0x0519) = 0x0009
JTX_LID10_CFG                       (0x051A) = 0x000A
JTX_LID11_CFG                       (0x051B) = 0x000B
JTX_LID12_CFG                       (0x051C) = 0x000C
JTX_LID13_CFG                       (0x051D) = 0x000D
JTX_LID14_CFG                       (0x051E) = 0x000E
JTX_LID15_CFG                       (0x051F) = 0x000F
JTX_SCR_L_CFG                       (0x0520) = 0x000F
JTX_F_CFG                           (0x0521) = 0x0001
JTX_K_CFG                           (0x0522) = 0x001F
JTX_M_CFG                           (0x0523) = 0x0000
JTX_CS_N_CFG                        (0x0524) = 0x000B
JTX_SCV_NP_CFG                      (0x0525) = 0x000F
JTX_JV_S_CFG                        (0x0526) = 0x002F
JTX_HD_CF_CFG                       (0x0527) = 0x0000
JTX_CHKSUM0_CFG                     (0x052B) = 0x0078
JTX_CHKSUM1_CFG                     (0x052C) = 0x0079
JTX_CHKSUM2_CFG                     (0x052D) = 0x007A
JTX_CHKSUM3_CFG                     (0x052E) = 0x007B
JTX_CHKSUM4_CFG                     (0x052F) = 0x007C
JTX_CHKSUM5_CFG                     (0x0530) = 0x007D
JTX_CHKSUM6_CFG                     (0x0531) = 0x007E
JTX_CHKSUM7_CFG                     (0x0532) = 0x007F
JTX_CHKSUM8_CFG                     (0x0533) = 0x0080
JTX_CHKSUM9_CFG                     (0x0534) = 0x0081
JTX_CHKSUM10_CFG                    (0x0535) = 0x0082
JTX_CHKSUM11_CFG                    (0x0536) = 0x0083
JTX_CHKSUM12_CFG                    (0x0537) = 0x0084
JTX_CHKSUM13_CFG                    (0x0538) = 0x0085
JTX_CHKSUM14_CFG                    (0x0539) = 0x0086
JTX_CHKSUM15_CFG                    (0x053A) = 0x0087
JTX_LANE_PDWN                       (0x053B) = 0x0000
JTX_LANE_PDWN2                      (0x053C) = 0x0000
JTX_LANE_ASSIGN1                    (0x053D) = 0x0010
JTX_LANE_ASSIGN2                    (0x053E) = 0x0032
JTX_LANE_ASSIGN3                    (0x053F) = 0x0054
JTX_LANE_ASSIGN4                    (0x0540) = 0x0076
JTX_LANE_ASSIGN5                    (0x0541) = 0x0098
JTX_LANE_ASSIGN6                    (0x0542) = 0x00BA
JTX_LANE_ASSIGN7                    (0x0543) = 0x00DC
JTX_LANE_ASSIGN8                    (0x0544) = 0x00FE
JTX_QBF_STATUS_REG                  (0x0547) = 0x002D
JTX_TEST_GEN_INV                    (0x0557) = 0x0000
CHIP_USR_PAT_1_7_0                  (0x0558) = 0x0000
CHIP_USR_PAT_1_15_8                 (0x0559) = 0x0000
CHIP_USR_PAT_2_7_0                  (0x055A) = 0x0000
CHIP_USR_PAT_2_15_8                 (0x055B) = 0x0000
CHIP_USR_PAT_3_7_0                  (0x055C) = 0x0000
CHIP_USR_PAT_3_15_8                 (0x055D) = 0x0000
CHIP_USR_PAT_4_7_0                  (0x055E) = 0x0000
CHIP_USR_PAT_4_15_8                 (0x055F) = 0x0000
SER_PARITY_RESET_EN1                (0x0560) = 0x0000
SER_PARITY_RESET_EN2                (0x0561) = 0x0000
SER_PARITY_ERR1                     (0x0564) = 0x0000
SER_PARITY_ERR2                     (0x0565) = 0x0000
PLL_ENABLE_CTRL                     (0x0570) = 0x0001
JESD_S_CFG                          (0x0591) = 0x0000
JESD_HD_CF_CFG                      (0x0592) = 0x0000
PWR_DN                              (0x05B0) = 0x0000
PWR_DN2                             (0x05B1) = 0x0000
DDC_SYNC_CTRL                       (0x0600) = 0x0002
DDC_SYNC_STATUS                     (0x0601) = 0x0000
DDC_TRIG_CTRL                       (0x0602) = 0x0000
CHIP_DP_MODE                        (0x0606) = 0x0020
CHIP_DEC_RATIO                      (0x0607) = 0x0000
CHIP_RES_0                          (0x0608) = 0x0000
CHIP_RES_1                          (0x0609) = 0x0000
CTRL_0_1_SEL                        (0x0620) = 0x0000
CTRL_2_SEL                          (0x0621) = 0x0000
OUT_FORMAT_SEL                      (0x0622) = 0x0000
OVR_STATUS                          (0x0623) = 0x0000
OVR_CLR                             (0x0624) = 0x0000
OUT_CHAN_SEL                        (0x0625) = 0x0000
OUT_RES                             (0x0626) = 0x0000
DDC_CTRL                            (0x0630) = 0x0000
DDC_DEC_CTRL                        (0x0631) = 0x0000
DDC_NCO_CTRL                        (0x0632) = 0x0000
DDC_PROFILE_CTRL                    (0x0633) = 0x0000
DDC_PHASE_INC0                      (0x0634) = 0x0000
DDC_PHASE_INC1                      (0x0635) = 0x0000
DDC_PHASE_INC2                      (0x0636) = 0x0000
DDC_PHASE_INC3                      (0x0637) = 0x0000
DDC_PHASE_INC4                      (0x0638) = 0x0000
DDC_PHASE_INC5                      (0x0639) = 0x0000
DDC_PHASE_OFFSET0                   (0x063A) = 0x0000
DDC_PHASE_OFFSET1                   (0x063B) = 0x0000
DDC_PHASE_OFFSET2                   (0x063C) = 0x0000
DDC_PHASE_OFFSET3                   (0x063D) = 0x0000
DDC_PHASE_OFFSET4                   (0x063E) = 0x0000
DDC_PHASE_OFFSET5                   (0x063F) = 0x0000
DDC_PHASE_INC_FRAC_A0               (0x0640) = 0x0000
DDC_PHASE_INC_FRAC_A1               (0x0641) = 0x0000
DDC_PHASE_INC_FRAC_A2               (0x0642) = 0x0000
DDC_PHASE_INC_FRAC_A3               (0x0643) = 0x0000
DDC_PHASE_INC_FRAC_A4               (0x0644) = 0x0000
DDC_PHASE_INC_FRAC_A5               (0x0645) = 0x0000
DDC_PHASE_INC_FRAC_B0               (0x0646) = 0x0000
DDC_PHASE_INC_FRAC_B1               (0x0647) = 0x0000
DDC_PHASE_INC_FRAC_B2               (0x0648) = 0x0000
DDC_PHASE_INC_FRAC_B3               (0x0649) = 0x0000
DDC_PHASE_INC_FRAC_B4               (0x064A) = 0x0000
DDC_PHASE_INC_FRAC_B5               (0x064B) = 0x0000
DDC_TRANSFER_CTRL                   (0x064C) = 0x0000
DDC_TRANSFER_STATUS                 (0x064D) = 0x0000
MOD_NCO_PHASE_ERROR_LOAD_REG0       (0x0650) = 0x0000
MOD_NCO_PHASE_ERROR_LOAD_REG1       (0x0651) = 0x0000
MOD_NCO_PHASE_ERROR_LOAD_REG2       (0x0652) = 0x0000
MOD_NCO_PHASE_ERROR_LOAD_REG3       (0x0653) = 0x0000
MOD_NCO_PHASE_ERROR_LOAD_REG4       (0x0654) = 0x0000
MOD_NCO_PHASE_ERROR_LOAD_REG5       (0x0655) = 0x0000
MOD_NCO_PHASE_ERROR_LOAD_REG6       (0x0656) = 0x0000
NCO_PHASE_ERROR_LOAD_STATUS         (0x0657) = 0x0000
DDC_PSW_0                           (0x065F) = 0x0000
DDC_PSW_1                           (0x0660) = 0x0000
DDC_PSW_2                           (0x0661) = 0x0000
DDC_PSW_3                           (0x0662) = 0x0000
DDC_PSW_4                           (0x0663) = 0x0000
DDC_PSW_5                           (0x0664) = 0x0000
DDC_ACTIVE_PHASE_INC0               (0x0665) = 0x0000
DDC_ACTIVE_PHASE_INC1               (0x0666) = 0x0000
DDC_ACTIVE_PHASE_INC2               (0x0667) = 0x0000
DDC_ACTIVE_PHASE_INC3               (0x0668) = 0x0000
DDC_ACTIVE_PHASE_INC4               (0x0669) = 0x0000
DDC_ACTIVE_PHASE_INC5               (0x066A) = 0x0000
DDC_ACTIVE_PHASE_OFFSET0            (0x066B) = 0x0000
DDC_ACTIVE_PHASE_OFFSET1            (0x066C) = 0x0000
DDC_ACTIVE_PHASE_OFFSET2            (0x066D) = 0x0000
DDC_ACTIVE_PHASE_OFFSET3            (0x066E) = 0x0000
DDC_ACTIVE_PHASE_OFFSET4            (0x066F) = 0x0000
DDC_ACTIVE_PHASE_OFFSET5            (0x0670) = 0x0000
TIMESTAMP_READ_CTRL                 (0x0671) = 0x0000
TIMESTAMP_COUNTER_REG0              (0x0672) = 0x0000
TIMESTAMP_COUNTER_REG1              (0x0673) = 0x0000
TIMESTAMP_COUNTER_REG2              (0x0674) = 0x0000
TIMESTAMP_COUNTER_REG3              (0x0675) = 0x0000
TIMESTAMP_COUNTER_REG4              (0x0676) = 0x0000
TIMESTAMP_COUNTER_REG5              (0x0677) = 0x0000
TIMESTAMP_COUNTER_REG6              (0x0678) = 0x0000
TIMESTAMP_COUNTER_REG7              (0x0679) = 0x0000
JTX_CLK                             (0x0681) = 0x0010
SYSREF_DELAY                        (0x0690) = 0x0000
TRIG_DELAY                          (0x0691) = 0x0000
TIMESTAMP_DELAY                     (0x0692) = 0x0000
SYSREF_RESYNC                       (0x0693) = 0x0000
SYSREF_CTRL                         (0x1508) = 0x0000
SYSREF_STATUS                       (0x1509) = 0x0064
LVDS_SEL                            (0x150A) = 0x0000
SPI_EN_DCS                          (0x150C) = 0x0000
SPI_EN_FDLY                         (0x150D) = 0x0000
SPI_TRM_FINE_DLY                    (0x150E) = 0x0000
SPI_TRM_SUPER_FINE_DLY              (0x150F) = 0x0000
SPI_SFDC_BYPASS                     (0x1510) = 0x0000
BKEND_TOP_GAIN_ADJ                  (0x1511) = 0x0000
SUPPLY_MON1                         (0x1512) = 0x003F
SUPPLY_MON2                         (0x1513) = 0x001F
SUPPLY_MON3                         (0x1514) = 0x0003
PDOWN_CTRL                          (0x1515) = 0x00FC
SPI_EN_FDLY_SYS                     (0x1516) = 0x0000
SPI_TRM_FINE_DLY_SYS                (0x1517) = 0x0000
SPI_TRM_SUPER_FINE_DLY_SYS          (0x1518) = 0x0000
SPI_SFDC_BYPASS_SYS                 (0x1519) = 0x0000
EN_VCM_MODE                         (0x151A) = 0x0001
SPI_NVG1                            (0x151B) = 0x0005
CLOCK_DETECT_CTRL                   (0x151D) = 0x0003
MCS_CTRL                            (0x151E) = 0x0000
MCS_SYSREF_IGNORE_COUNT             (0x1521) = 0x0000
USER_CTRL_TRANSFER                  (0x1600) = 0x0000
CAL_CONTROL                         (0x1601) = 0x0000
MAX_TEMPERATURE_LSB                 (0x1609) = 0x00FF
MAX_TEMPERATURE_MSB                 (0x160A) = 0x003D
MIN_TEMPERATURE_LSB                 (0x160D) = 0x0015
MIN_TEMPERATURE_MSB                 (0x160E) = 0x003A
MCS_MODE                            (0x1621) = 0x0000
MCS_CTRL                            (0x1622) = 0x0000
MCS_CALC_TIME_DIFF1                 (0x1623) = 0x0000
MCS_CALC_TIME_DIFF2                 (0x1624) = 0x0000
MCS_CALC_TIME_DIFF3                 (0x1625) = 0x0000
MCS_CALC_TIME_DIFF4                 (0x1626) = 0x0000
MCS_KNOWN_SYSREF_PERIOD1            (0x1627) = 0x0000
MCS_KNOWN_SYSREF_PERIOD2            (0x1628) = 0x0000
MCS_KNOWN_SYSREF_PERIOD3            (0x1629) = 0x0000
MCS_SAMPLE_CLK_PERIOD1              (0x162D) = 0x0000
MCS_SAMPLE_CLK_PERIOD2              (0x162E) = 0x0000
MCS_SAMPLE_CLK_PERIOD3              (0x162F) = 0x0000
MCS_SAMPLE_CLK_PERIOD4              (0x1630) = 0x0000
MCS_PHASE_SLIP_MODE                 (0x1636) = 0x0000
    

    





    
    
    
        Fullscreen
        jesd204_regs_normal_mode.txt
        Download
    
    
    
    ************************JESD 0***********************
        ILA Support(0x08) = 0x1
        Scrambling(0x0C) = 0x0
        SYSREF Handling(0x10) = 0x1
        Test Modes(0x18) = 0x0
        Link Error Status(0x1C) = 0x924924
        Octets per Frame(0x20) = 0x1
        Frames per Multiframe(0x24) = 0x1F
        Lanes in Use(0x28) = 0xFF
        Subclass Mode(0x2C) = 0x0
        RX Buffer Delay(0x30) = 0x0
        Error Reporting(0x34) = 0x1
        Sync Status(0x38) = 0x1
        Debug Status(0x3C) = 0xEEEEEEEE
        Link Error Counts:0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0
*********************************************************
************************JESD 1***********************
        ILA Support(0x08) = 0x1
        Scrambling(0x0C) = 0x0
        SYSREF Handling(0x10) = 0x1
        Test Modes(0x18) = 0x0
        Link Error Status(0x1C) = 0x924924
        Octets per Frame(0x20) = 0x1
        Frames per Multiframe(0x24) = 0x1F
        Lanes in Use(0x28) = 0xFF
        Subclass Mode(0x2C) = 0x0
        RX Buffer Delay(0x30) = 0x0
        Error Reporting(0x34) = 0x1
        Sync Status(0x38) = 0x1
        Debug Status(0x3C) = 0xEEEEEEEE
        Link Error Counts:0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0
*********************************************************
    

    





    
    
    
        Fullscreen
        jesd204_regs_test_mode.txt
        Download
    
    
    
    ************************JESD 0***********************
        ILA Support(0x08) = 0x1
        Scrambling(0x0C) = 0x0
        SYSREF Handling(0x10) = 0x1
        Test Modes(0x18) = 0x0
        Link Error Status(0x1C) = 0x0
        Octets per Frame(0x20) = 0x1
        Frames per Multiframe(0x24) = 0x1F
        Lanes in Use(0x28) = 0xFF
        Subclass Mode(0x2C) = 0x0
        RX Buffer Delay(0x30) = 0x0
        Error Reporting(0x34) = 0x1
        Sync Status(0x38) = 0x0
        Debug Status(0x3C) = 0x0
        Link Error Counts:0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0
*********************************************************
************************JESD 1***********************
        ILA Support(0x08) = 0x1
        Scrambling(0x0C) = 0x0
        SYSREF Handling(0x10) = 0x1
        Test Modes(0x18) = 0x0
        Link Error Status(0x1C) = 0x0
        Octets per Frame(0x20) = 0x1
        Frames per Multiframe(0x24) = 0x1F
        Lanes in Use(0x28) = 0xFF
        Subclass Mode(0x2C) = 0x0
        RX Buffer Delay(0x30) = 0x0
        Error Reporting(0x34) = 0x1
        Sync Status(0x38) = 0x0
        Debug Status(0x3C) = 0x0
        Link Error Counts:0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0
*********************************************************
    

    


    

    Any insights on what may be wrong or how to troubleshoot would be extremely helpful. Thanks in advance.
    

    Mark
    
										

    
				Posted wrong screenshot of example where all eye diagrams are open.
    
[edited by: mgarrett at 3:45 PM (GMT -4) on 12 Sep 2021]
				
    
					
    

				
				
		
    
			
						
									
									
						
						
			
			
			
			
		
    

        
        

					
    
			
    


    


	















    
	
    
	
    
					



			


				
	









	
      
	

    • 
	
      



	
		
	
	



      
	
      
		
      
							
					
      
		
      
			
													0
							
			
				
									
							        
			
			
			
      •  Analog Employees  
      
            
			                            
                        
                on Sep 18, 2021 5:39 AM
            
            
					
      
	
      

		
		
      
					
      Hi Mark,
      

      Thanks for your interest in AD9213. I'm sorry about the slow reply. One thing to note is that the polarity is flipped on the board for some of the JESD outputs. This was for board layout considerations.
      

      My bench is currently inoperable due to a an office move. I'll try to look into your question in a few days.
      

      I'm sorry about the delay.
      

      Doug
      
			
      

		
		
		
		
	
      
	
      
		
      
			
		
      
	
      
	
      
		
						
						
				
						
				
				
		
		
      
			
		
      
	
      

      

      • 

	

    • 
	
      



	
		
	
	



      
	
      
		
      
							
					
      
		
      
			
													0
							
			
				
									
							        
			
			
			
        
            
			                            
                        
                on Sep 22, 2021 8:01 PM
            
            
												
						in reply to DougI
					
									
        
	
        

		
		
        
					
        Doug,
        

        Thanks for the response.  No worries about the delay. Just to clarify, the board I'm having issues with is the http://www.hitechglobal.com/FMCModules/12-bitADC_10Gsps.htm. I do have the https://www.analog.com/en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/eval-ad9213.html and it works as expected via the ACE software. I have compared the AD9213 registers from the EVAL-AD9213 board with the HiTech board and there aren't any glaring discrepancies between configurations other than JESD parameters.  Although, I did not find a way to generate a test pattern with the ACE software.  I will note that I am unable to use the EVAL-AD9213 on my FPGA board as unfortunately not all of the FMC pins are traced back to the FPGA.
        

        The HiTech board has an HMC7044 for the JESD clocks and I've verified that they are programmed correctly.  I've also confirmed that the AD9213 sampling clock is 10GHz.
        

        My two test cases right now are: test mode (alternating checkerboard, syncinb ) and normal mode (syncinb set to normal).
        

        Looking forward to hearing your inputs.
        

        Thanks,
        

        Mark
        
			
        

		
		
		
		
	
        
	
        
		
        
			
		
        
	
        
	
        
		
						
						
				
						
				
				
		
		
        
			
		
        
	
        

        

        • 

	

      • 
	
        



	
		
	
	



        
	
        
		
        
							
					
        
		
        
			
													0
							
			
				
									
							        
			
			
			
        •  Analog Employees  
        
            
			                            
                        
                on Oct 5, 2021 4:56 AM
            
            
												
						in reply to mgarrett
					
									
        
	
        

		
		
        
					
        Hi Mark,
        

        I apologize for the delayed response.
        

        Thank you for sharing additional details. I know very little about the HiTechGlobal board, but it appears that the AD9213 on the HiTech board gets its sample clock from the HMC7044. If that is the case, are you able to apply a 10GHz clock from an external source?
        

        For more in depth questions related to the HiTechGlobal board, you'll need to go to HiTechGlobal for support.
        

        In ACE, there is a Register Debugger function which allows you to write specific registers. Using this you should be able to try the test patterns on the AD9213 evaluation board.
        

        Thank you.
        

        Doug
        
			
        

		
		
		
		
	
        
	
        
		
        
			
		
        
	
        
	
        
		
						
						
				
						
				
				
		
		
        
			
		
        
	
        

        

        • 

	

      • 
	
        



	
		
	
	



        
	
        
		
        
							
					
        
		
        
			
													0
							
			
				
									
							        
			
			
			
          
            
			                            
                        
                on Oct 5, 2021 6:35 AM
            
            
												
						in reply to DougI
					
									
          
	
          

		
		
          
					
          Hi Doug,
          

          No worries, we're all busy :). The HiTech board does provide the hardware needed for a 10GHz clock and I have verified that it is correct.  As an update, I did eventually get past the test pattern issue by ignoring the instruction to disable SYNCINB on pg. 70 of the AD9213 datasheet.  In my scenario, I think the sync handshake is needed as two Xilinx JESD204 cores are needed for 16 lane data and without the CGS/ILAs stage, the test pattern never aligned.  Once I set JTX_LINK_CTRL2 == 0, the test pattern came through correctly.
          

          If I can amend another question to this thread, I would like to ask about the output data format.  Now that I am able to pull data off of the ADC (with reasonable certainty), I'm struggling to demap the data correctly.  I've noted that some of the ADI AD9213 EVM's serdes outputs are inverted but I do not see any inversions on the schematics provided by Hitech (a schematic is the only BSP provided by the way).  However, I am able to see output that looks close but isn't quite right.  For example, here is a the output of 30MHz sine (note the time domain image is zoomed but the FFT is not):
          

           
          

          Any ideas about what might be causing the data issues and/or more details about data format would be extremely helpful. 
          

          

          Thanks again,
          

          Mark
          
			
          

		
		
		
		
	
          
	
          
		
          
			
		
          
	
          
	
          
		
						
						
				
						
				
				
		
		
          
			
		
          
	
          

          

          • 

	

        • 
	
          



	
		
	
	



          
	
          
		
          
							
					
          
		
          
			
													0
							
			
				
									
							        
			
			
			
          •  Analog Employees  
          
            
			                            
                        
                on Oct 5, 2021 10:04 AM
            
            
												
						in reply to mgarrett
					
									
          
	
          

		
		
          
					
          Hi Mark,
          

          Great job on the progress.
          

          Regarding the output data format, we have a Frame Mapping Table Generator that tells you how the data comes out for a given JESD204B configuration. It is here: https://www.analog.com/en/license/licensing-agreement/jesd204x-frame-mapping-table-generator.html .
          

          Also, if it would help I can request that sample FPGA capture code be sent to you to show what we do in the FPGA, though we cannot include the Xilinx JESD204B IP.
          

          Please let me know if the Frame Mapping Table Generator gives you what you are looking for.
          

          Thanks,
          

          Doug
          
			
          

		
		
		
		
	
          
	
          
		
          
			
		
          
	
          
	
          
		
						
						
				
						
				
				
		
		
          
			
		
          
	
          

          

          • 

	

        • 
	
          



	
			
		
	



          
	
          
		
          
							
					
          
		
          
			
													0
							
			
				
									
							        
			
			
			
            
            
			                            
                        
                on Oct 10, 2021 8:32 PM
            
            
												
						in reply to DougI
					
									
            
	
            

		
		
            
					
            Doug,
            

            Thanks for the insights and suggestions.  There were two issues with the scrambled sine wave from above. 
            

            1) Using two separate Xilinx JESD cores under the guidance of https://support.xilinx.com/s/article/71575?language=en_US appears to require subclass 1.  Using subclass 0 with this configuration results in out of order data samples in the output.  I haven't determined why subclass 0 doesn't work quite right but switching to subclass 1 results in the expected data.
            

            2) The demapping appeared in the  2 Xiling JESD rx_tdata outputs in an interleaved pattern that spreads across the two 256 bit arrays.  Something like this (s0 == sample 0, 32 samples per clock):
            

            rx_tdata_0[255:0] = [ s23 s7 s22 s6 s21 s5 s20 s4 s19 s3 s18 s2 s17 s1 s16 s0]
            rx_tdata_1[255:0] = [ s31 s15 s30 s14 s29 s13 s28 s12 s27 s11 s26 s10 s25 s9 s24 s8]
            

            Thanks again for the help!
            

            Mark
            
			
            

		
		
		
		
	
            
	
            
		
            
			
		
            
	
            
	
            
		
						
						
						
						
				
				
		
		
            
			
		
            
	
            

            

            • 

	

          • 
	
            



	
		
	
	



            
	
            
		
            
							
					
            
		
            
			
													0
							
			
				
									
							        
			
			
			
              
            
			                            
                        
                on Jan 23, 2022 2:41 PM
            
            
					
              
	
              

		
		
              
					
              Hi Mark,
              

              Could you tell me which PLL did you use for the GTY transceiver, CPLL or QPLL? I'm using the same HTG board as yours. In my case, when I used CPLL, I saw that the CPLL did not lock, but the QPLL did. However, when the QPLL locked, I did not see any K28.5 character on the gt#_rxdata lanes.
              

              I'm not sure if I configured the HMC7044 and ADF4371 properly. Could you share your HMC7044 and ADF4371 register files to me? That would be very helpful for me. Thank you so much!!!
              
			
              

		
		
		
		
	
              
	
              
		
              
			
		
              
	
              
	
              
		
						
						
				
						
				
				
		
		
              
			
		
              
	
              

              

              •