I'm currently developing a prototype in which I plan to use the AD9235-20. I do, however, have a few questions that I would like to solve before continuing with the development:
1) The AD9235's datasheet suggests using a 3V supply for AVDD. However, in the specifications, the AVDD pin is said to accept voltages in the range [2.7, 3.6]. My idea is to use a low noise 3.3V regulator to both power the ADC (AVDD) and serve as a CMOS reference for the output buffers (DRVDD). Is this feasible?
2) Regarding the clock, I have chosen the ECS-TXO-2520MV. In my application, even though the AD9235-20 can output data at 20 MSPS, I plan to use a 10 MHz crystal to set the sampling frequency and the output data rate to this frequency. The idea is to oversample a 200 kHz sine wave (50 data points/period).
The crystal that I have chosen, according to the formulas given in the datasheet, should be good enough, but I have included my calculations below, as I am not entirely confident about them:
% ADC Specs
tj_adc = 0.5e-12; % ps RMS
SNR = 70.8; % dBc
F_sample = 10e6; % Hz
% Crystal Specs
tj_clock_source = 0.254e-12;
t_jitter_total = sqrt((tj_adc)^2 + (tj_clock_source)^2)
SNR_max_clk = -20*log10(2*pi*Fsample*t_jitter_total)
SNR_max = -20*log10(sqrt((10^(-SNR/20))^2 + (10^(-SNR_max_clk/20))^2)) %% 70.73 dBc
These calculations yield a 0.06 dBc SNR loss due to the chosen crystal. Have the calculations been performed correctly?
3) Finally, regarding the output clock, the datasheet indicates that the typical Output Delay time is 3.5 ns. Knowing that I will be running the ADC at 10 MHz, would it make sense to add a logic buffer to the clock to have a delayed version of it at the output stage (To correctly acquire the data)?
Thanks in advance,