AD9467 Incorrect Behavior in Normal Operation, Urgent Help Needed

In our  custom designed board, we have digitizer boards based on AD9467 interfacing to FPGA. Many of the boards work correctly. But many of the boards doesn't work for the AD9467 normal operation. We verified that Data samples from AD9467 device are being captured correctly inside the FPGA by running ADC into Test Modes of Checkerboard and One/Zero Word Toggle. We don't see any setup/hold violations happening. But on the failing boards, we observed that when ADC is switched to normal operation mode, the captured output waveform is distorted as if comparators inside the ADC are not working correctly to provide the correct output digital code. e.g. in the attached waveform capture named  ADC_CHA_1000mVpp_1MHz_Analog_Plot_2_Bit9_Incorrect.jpg , we see that Bit 9 data is in correct. 

In the attached file ADC_CHA_1000mVpp_1MHz_Analog_Plot_2_Bit9_Incorrect.jpg, for initial 220 samples I modified the ADC samples using following equation in order to focus on ADC data output bit position 9. 

for i = 133:220
dout(i) = dout(i)+ 512;
end
for i = 7:100
dout(i) = dout9i) - 512;
end

The Red color is the modified waveform overlapped with the original waveform (captured from failing board) in blue color.

Your urgent supported is greatly appreciated in order to solve the problem. 

Thank you

Kuldip



updated text
[edited by: Kuldip at 11:50 PM (GMT -4) on 17 Aug 2021]
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  • 0
    •  Analog Employees 
    on Aug 18, 2021 1:01 PM

    Can you please verify that the supply voltages are correct? The correct voltages are listed in Table 1 of the datasheet. Another trouble shooting step would be to enable one of the test modes to make sure that the output data is being received properly.

  • Hi Alex,

         Supply Voltages are verified to be correct. In the above attached waveform captures of ADC Test Mode=4(Checkerboard) and ADC Test Mode=7(One/Zero Word Toggle), the data received on the FPGA is correctly captured. We ran these tests for very long time and there are no errors for the data received. 

         The problem is seen when ADC is switched into normal operation mode. 

    Thanks

    Kuldip

Reply
  • Hi Alex,

         Supply Voltages are verified to be correct. In the above attached waveform captures of ADC Test Mode=4(Checkerboard) and ADC Test Mode=7(One/Zero Word Toggle), the data received on the FPGA is correctly captured. We ran these tests for very long time and there are no errors for the data received. 

         The problem is seen when ADC is switched into normal operation mode. 

    Thanks

    Kuldip

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