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One lane mode AD9681 HSC-ADC-EVALEZ

Hello support team,

I am working with AD9681 + HSC-ADC-EVALEZ. I've already have the HDL code for configure it. 

But in the code I have, there is only option for two lane mode. 

Could I ask the HDL code part for one lane mode? 

Thank you,

HOANG

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  • Hi Dougl,

    Thank you. 

    Could you check the PIN to me? It seem something wrong about DCO1 and DCO2. Thank you

    HOANG 

  • Hi HOANG,

    Would you please explain your question/concern a bit more? Are you saying that the FPGA code shows DCO1 is connected to H11 and H10 instead of DCO2?

    This is what I see in the code:
    AD9681 code
    NET lvds_dco2_p LOC = H11 | IOSTANDARD = LVDS_25 | DIFF_TERM = TRUE ; # LA00
    NET lvds_dco2_n LOC = H10 | IOSTANDARD = LVDS_25 | DIFF_TERM = TRUE ;


    AD9249 code
    NET lvds_dco2_p LOC = H11 | IOSTANDARD = LVDS_25 | DIFF_TERM = TRUE ;
    NET lvds_dco2_n LOC = H10 | IOSTANDARD = LVDS_25 | DIFF_TERM = TRUE ;

    Maybe I am misunderstanding your question.

    Thanks,

    Doug

  • Thanks Dougl, I think I know the problem. It seem I see the two code version of AD9681. I just check the last one.

    I have another question. "I want to put some process after "capturing the data" and transfer the result to pc. could I do it with 8 parallel channel at the same time?

    Thanks,