One lane mode AD9681 HSC-ADC-EVALEZ

Hi HOANG,

Thank you for your interest in AD9681.

The FPGA program for AD9681 is hard-coded for 2-lane mode. The AD9249 is the 16 channel 1-lane version of the AD9681.

I'll request that the sample FPGA code for AD9249 and HSC-ADC-EVALEZ be sent to you.

Thanks,

Doug

Hi Dougl,

Thank you. 

Could you check the PIN to me? It seem something wrong about DCO1 and DCO2. Thank you

HOANG 

Hi HOANG,

Would you please explain your question/concern a bit more? Are you saying that the FPGA code shows DCO1 is connected to H11 and H10 instead of DCO2?

This is what I see in the code:
AD9681 code
NET lvds_dco2_p LOC = H11 | IOSTANDARD = LVDS_25 | DIFF_TERM = TRUE ; # LA00
NET lvds_dco2_n LOC = H10 | IOSTANDARD = LVDS_25 | DIFF_TERM = TRUE ;

AD9249 code
NET lvds_dco2_p LOC = H11 | IOSTANDARD = LVDS_25 | DIFF_TERM = TRUE ;
NET lvds_dco2_n LOC = H10 | IOSTANDARD = LVDS_25 | DIFF_TERM = TRUE ;

Maybe I am misunderstanding your question.

Thanks,

Doug

Thanks Dougl, I think I know the problem. It seem I see the two code version of AD9681. I just check the last one.

I have another question. "I want to put some process after "capturing the data" and transfer the result to pc. could I do it with 8 parallel channel at the same time?

Thanks,