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ad9625 sysref in subclass0 on FMCADC3


I need to run the ad9625 on my fmcadc3 (Rev-A) in subclass 0 mode with the "timestamp" bit added on to the output data. I have all of the lanes up in DATA mode and the analog data from the ADC is transferring properly, but the sysref bit is not getting added on to the sample data. Upon further inspection, I believe the ADC is never seeing the SYSREF signal in the first place. I've set register 0x08A to 0x22 as indicated in the datasheet and 0x72 to 0x0B | 0x02 << 6 to enable both control bits. To start, I tried setting AD9625_REG_SYSREF_CONTROL (0x03A) to "continuous" mode, but I have also tried it in "next" mode (setting the register to 0x06). After setting the sysref control to "next" the datasheet states that the first bit of the 0x03A register will clear on the next valid edge of the sysref. It never clears for me, so I assume the device is not detecting the sysref edge.

I'm generating the SYSREF signal from the SYSREF+ and SYSREF- (J101 and J103, which are connected to the FMC connector on the board) and connecting them via short sma cables to DUT_SYSREF+ and DUT_SYSREF- (J102 and J104). The signal from the FPGA is LVDS, so it should produce a sufficient voltage swing across the 100 ohm resistor on the fmcadc3.

Is there something I'm missing about properly setting up the SYSREF registers or stimulus? I'm at a bit of a loss.

Thank you for your time,