Does the LTC support multichip synchronization in JESD subclass 0 as per this link?
One advantage of implementing deterministic latency is that it provides a means by which multichip synchronization can take place. However, it is not necessary to implement deterministic latency to achieve multichip synchronization. The JESD204 standard makes provisions for control bits to be added to sample data in order to convey information about the sample from the transmitter to the receiver. In ADC applications, it is possible to use a control bit as a time stamp to flag a sample that occurs coincidently with an external reference. If using a subclass 1 device in subclass 0 operating mode, this can be accomplished using the SYSREF input.