I'm trying to clock my FMCADC3 (which is connected to my zc706) from an external pll (ADF4350 EB1Z evaluation board set to 2.5 GHz). I did some rework on the FMCADC3 to install resistor R301 and capacitor on C301 as indicated in the schematic https://wiki.analog.com/_media/resources/eval/user-guides/02_039614a.pdf. The external ADF4350 is clearly locked and producing a signal. However, when I read the PLL lock register (0x00A) from the ad9625, it is 0x00, indicating that the internal PLL is not locked. The SPI communication is clearly working to the board (I can read the chip ID correctly), and I've configured all of the registers the same as in the fmcadc2 no-os reference design on the Analog devices github.
What might be causing the PLL in the ad9625 to fail to lock? Is the lock of this PLL in any way dependent upon the JESD interface to the FPGA or is it only dependent on the reference clock input?
Thanks in advance for your help!