FMCADC3 with an external clock fails to lock

Hello all,

I'm trying to clock my FMCADC3 (which is connected to my zc706) from an external pll (ADF4350 EB1Z evaluation board set to 2.5 GHz). I did some rework on the FMCADC3 to install resistor R301 and capacitor on C301 as indicated in the schematic https://wiki.analog.com/_media/resources/eval/user-guides/02_039614a.pdf. The external ADF4350 is clearly locked and producing a signal. However, when I read the PLL lock register (0x00A) from the ad9625, it is 0x00, indicating that the internal PLL is not locked. The SPI communication is clearly working to the board (I can read the chip ID correctly), and I've configured all of the registers the same as in the fmcadc2 no-os reference design on the Analog devices github.

What might be causing the PLL in the ad9625 to fail to lock? Is the lock of this PLL in any way dependent upon the JESD interface to the FPGA or is it only dependent on the reference clock input?

Thanks in advance for your help!

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  • In case someone else stumbles upon a similar issue, I took two steps to stabilize the ad9625 internal pll using the ADF4350EB1Z as the clock source. Since the output of the ADF4350 is already AC coupled, I removed all of the AC coupling capacitors on the fmcadc3 and replaced them with solder bridges. Next, I used solder bridges to bypass the transformer with the differential signal. I removed R301 and R310 and placed a 100 ohm resistor on R315. I configured the ADF4350EB1Z to send +2dbm. The other critical step was to reset the ad9625 after the ADF4350 was locked as indicated on page 71 of the datasheet. The ad9625 pll status register now shows a locked state. Hope this helps someone else avoid the headache!

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  • In case someone else stumbles upon a similar issue, I took two steps to stabilize the ad9625 internal pll using the ADF4350EB1Z as the clock source. Since the output of the ADF4350 is already AC coupled, I removed all of the AC coupling capacitors on the fmcadc3 and replaced them with solder bridges. Next, I used solder bridges to bypass the transformer with the differential signal. I removed R301 and R310 and placed a 100 ohm resistor on R315. I configured the ADF4350EB1Z to send +2dbm. The other critical step was to reset the ad9625 after the ADF4350 was locked as indicated on page 71 of the datasheet. The ad9625 pll status register now shows a locked state. Hope this helps someone else avoid the headache!

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