For the ENC+/- inputs on an LTC2184, the data sheet shows two 0.1uF caps (series) as recommended termination for LVDS drive mode (Figure 13, on p. 22). It also states that the inputs are internally biased to 1.2V, and that ENC- should stay > 200mV above ground to avoid falsely triggering single ended mode.
I plan on driving this from a Xilinx FPGA with outputs configured for LVDS, 1.8V. With the above mentioned bias, ENC- should be at 300mV, so that condition is met.
Why is there no parallel termination resistor shown in Figure 13 of the LTC2184 data sheet?
Shouldn't the input be something more like one of these: