I am using the following JESD204B setting from Table 25 from the datasheet:
- L = 16
- M = 1
- F = 1
- S = 8
- HD = 1
- N = 12
- N' = 16
- CS = 3
I am able to capture data successfully on the JESD204B receiver in my FPGA. I am unable to receive any control bits.
I am setting the following registers with respect to enable control bits:
- register 0x509=0x1, DFORMAT output (Register 0x620 and Register 0x621).
- register 0x524=0xcb, CS=3, N=12
- register 0x620=0x01, control bit1=tied low, control bit2 = overrange
- register 0x621=0x05, control bit2 = sysref
Is there anything in my configuration that is incorrect or are there any other registers that I should be setting to enable control bits?